PAC1721 datasheet(27/92 Pages) MICROCHIP

27 / 92 page

 2026 Microchip Technology Inc. and its subsidiaries

DS-20007088A-page 27

PAC1721

5.0

SMBUS AND I2C COMMUNICATIONS PROTOCOLS

PAC1721 communicates over a two-wire bus with a

Controller using SMBus or I2C. Figure 5-1 shows a

detailed SMBus timing diagram.

Stretching of the SMBus clock signal is supported.

However, PAC1721 does not stretch the clock signal.

FIGURE 5-1:

SMBus Timing Diagram.

5.1

Addressing and Control Bits

The following section describes SMBus and I2C

addressing and their control bits. The address of

PAC1721 is defined by the connections of pins A0 and

A1 as shown in Table 5-1. The control bits follow the

SMBus and I2C protocol standards.

5.1.1

SMBUS ADDRESS AND RD/WR BIT

The SMBus address byte consists of the 7-bit target

address followed by a 1-bit RD/WR indicator. If this

RD/WR bit is at logic ‘0’, the SMBus is writing data to

the target device. If this RD/WR bit is at logic ‘1’, the

SMBus host is reading data from the target device.

Power-on Reset (POR) Condition:

On power-up, PAC1721 does not have any Alert, GPIO

or Slow functionality.

Send an I2C command to set the address. The address

is defined by the hardware connections between pins

A0 and A1 (see Table 5-1) once the I2C Serial Data

(SDA) and Serial Clock (SCL) completes three cycles.

I2C SDA acts as START condition. The initial command

can be any command that is supported by PAC1721.

The device first sets its address and then executes the

received commands.

Multifunction pin. When pulled up to VDD,

pin A0 or A1 can be programmed to operate

as SLOW, GPIO or ALERT pin.

Multiple PAC1721 or other devices can share the same

I2C bus without any functional differences. If the host

command is issued to another IC on the bus, PAC1721

still defines its address based on that command. To

detect the SDA condition, the SDA hold time must be

longer than the spike suppression period:

tHD:DAT > tSP

After the initial command, the I2C address is set and

cannot be changed until the next POR event (VDD or

PWRDN pin) occurs. Afterwards, pins A0/A1 are either

high impedance or operate as defined in Table 5-1. The

default functions are defined in the CONTROL register.

tHIGH

tSU:STO

tSU:STA

tSU:DAT

tHD:STA

tRISE

tHD:DAT

SMBCLK

SMBDAT

START Condition

STOP Condition

tFALL

START Condition

STOP Condition

VIH_MIN + 0.15V

VIL_MAX –0.15V

VIH_MIN + 0.15V

VIL_MAX –0.15V

tLOW

tBUF

Note:

IDD is slightly higher during this initial

address selection. This is caused by an

internal oscillator that is active while the

address is determined.

TABLE 5-1:

ADDRESS SELECT

A1 PIN

A0 PIN

SMBUS

ADDRESS

GND

1000 000b

GND

VDD Pull-up(*)

1000 001b

GND

SDA

1000 010b

GND

SCL

1000 011b

VDD Pull-up(*)

GND

1000 100b

VDD Pull-up(*)

1000 101b

VDD Pull-up(*)

SDA

1000 110b

VDD Pull-up(*)

SCL

1000 111b

SDA

GND

1001 000b

SDA

VDD Pull-up(*)

1001 001b

SDA

1001 010b

SDA

SCL

1001 011b

SCL

GND

1001 100b

SCL

VDD Pull-up(*)

1001 101b

SCL

SDA

1001 110b

SCL

1001 111b

PAC1721 Datasheet(PDF) 27 Page - Microchip Technology

PAC1721 Datasheet(HTML) 27 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92

Datasheet Download

Link URL