PAC1721 datasheet(16/92 Pages) MICROCHIP

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PAC1721

DS-20007088A-page 16

 2026 Microchip Technology Inc. and its subsidiaries

4.2.6

SLEEP STATE

The Sleep state is a lower power state than the Active

state, during which PAC1721 draws a supply current,

ISLEEP, (5 µA, typical) from pin VDD. During this state,

registers retain their values and do not reset.

PAC1721 enters the Sleep state when a Refresh or

Refresh_V command follows a write to the CONTROL

sampling only after selecting a new sample mode. To

force PAC1721 out of the Sleep state:

Select a new sample mode/rate by setting the

SAMPLE_MODE[3:0] bits in the CONTROL

Issue a Refresh or Refresh_V command to apply

the new sample mode.

PAC1721 does not enter the Sleep state based on any

other parameters, such as static conditions on the

SMBus pins. If the SMBus Timeout feature is enabled,

it functions in both Sleep and Active states.

To enter Sleep state, set the SAMPLE_MODE[3:0] bits

in the CONTROL register to 1110b or 1111b.

4.2.7

POWER-DOWN STATE

The only way to enter the Power-down state is to pull

down the PWRDN pin. In this state, all PAC1721

circuits, including the SMBus pins, are inactive and the

device is in a state of minimum power dissipation.

In the Power-down state, PAC1721 does not retain any

data, be it register configuration or measurement data.

When the PWRDN pin is pulled high, sampling, power

integration and accumulation resume using the default

The initial request for measurement data must be done

tINT_T (time to first communications; 20 ms, maximum)

after POR with a Refresh or Refresh_V command. POR

occurs when VDD exceeds VPOR (1.2 V, typical) or when

the PWRDN pin is pulled high.

The POR bit in the SMBUS_SETTINGS register is set

to 1b on POR events. To determine that a POR event

occurred using this bit, follow these steps:

1. After the initial POR event, clear the POR bit.

2. Poll the SMBUS_SETTINGS register to check if the

POR bit is indeed cleared.

3. If the POR bit is set to 1b when polling the register,

then a POR event occurred and PAC1721 requires

reprogramming, unless the objective is to operate the

device using the default configuration for all registers.

4.2.8

SLOW SAMPLE MODE

Pins A0 and A1 are multifunction pins when pulled to

VDD through a resistor. When programming pin A0 or

A1 for the Slow sample mode, the selected pin is now

considered the SLOW pin. If the SLOW pin is pulled

high, PAC1721 samples at 8 sps. Regardless of the

configured sample rate, this new Slow sample rate

takes effect on the next conversion cycle. If a conver-

sion cycle is in progress when pulling the SLOW pin

high, the Slow sample rate takes effect after the current

conversion cycle completes.

To configure pin A0 or A1 as the SLOW pin, set the

following bit in the CONTROL register:

•A0 → SLOW_ALERT0[1:0] = 11b

•A1 → GPIO_ALERT1[1:0] = 11b

4.2.8.1

Interaction with ALERT0/1

Pin A0 can function as the ALERT0 pin, while pin A1

can operate as the ALERT1 pin. If the Alert function is

enabled for pin A0 or A1, that pin can no longer control

the active conversion.

Alert conditions include overvoltage, undervoltage,

overcurrent, undercurrent, overpower, step limit,

accumulator overflow and accumulator count overflow.

If an alert condition is assigned to the A0 or A1 pin,

sampling proceeds at the programmed rate (or the

default rate of 1,024 sps if not changed). For more

details, see Section 4.10.

To configure pin A0 or A1 as an ALERT pin, set the

following bit in the CONTROL register:

•A0 → SLOW_ALERT0[1:0] = 00b

•A1 → GPIO_ALERT1[1:0] = 00b

If pin A0 or A1 is set to operate as ALERT pin and not

as SLOW pin, the Slow sample rate of 8 sps can be

selected by setting the SAMPLE_MODE[3:0] bits in the

CONTROL register to 0101b. Other sample rates are

available. For more details, see Register 6-2.

If PAC1721 operates in one of the Single-shot sample

modes and the SLOW pin is pulled high, sampling

starts one band gap start-up cycle after the SLOW pin

is pulled high. This lasts for a maximum of 5 ms.

If PAC1721 is in the Sleep state, pulling the SLOW pin

high does not trigger the device to initiate sampling.

Note 1: The Power-down state is available only

on the 10-Lead VDFN package.

2: Maximum voltage on this pin is VDD.

Do not pull this pin up to voltages that

exceed VDD.

Note:

While both A0 and A1 pins can be set as

SLOW pins, A0 precedes A1. If A0 is set

as SLOW pin and pulled high, PAC1721

enters Slow sample mode, regardless

how pin A1 is configured or controlled.

Note:

The same pin (A0 or A1) cannot be set

to operate as both SLOW and ALERT

pin simultaneously.

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