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PAC1721 Datasheet(PDF) 63 Page - Microchip Technology |
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PAC1721 Datasheet(HTML) 63 Page - Microchip Technology |
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63 / 92 page ![]() 2026 Microchip Technology Inc. and its subsidiaries DS-20007088A-page 63 PAC1721 REGISTER 6-24: CONTROL_ACT (ADDRESS 17H) R-0 R-0 R-1 R-0 R-0 R-1 R-0 R-1 SAMPLE_MODE[3:0] GPIO_ALERT1[1:0] SLOW_ALERT0[1:0] bit 15 bit 8 R-0 R-0 R-0 R-0 R-0 R-0 R-0 AVERAGE[2:0] AA ACC_CONFIG[1:0] AUTO_REFRESH[1:0] bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as 0 -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared X = Bit is unknown This register contains copy of the CONTROL register. This register reflects the settings that are currently active. The values in the CONTROL register can be programmed, but not yet activated by a Refresh (any) command, while the values in the CONTROL_LAT register are the settings active before receiving a Refresh (any) command. This register allows to determine the actual active settings. This register becomes valid when the results registers are valid following a Refresh (any) command issued after a conversion cycle completes. However, when changing the sample rate followed by a Refresh command, the sample rate does not change until the current conversion cycle completes. In some cases, this can cause a delay before the conversion cycle and the CONTROL_ACT register update. This delay can be variable, depending on when in the conversion cycle the Refresh command is executed. bit 15:12 SAMPLE_MODE[3:0]: Selects one of the sample modes listed below. These modes are exclusive – only one mode can be set at any given time. One of the sample rate options is Sleep state for when no sampling occurs. When switching sample modes during a conversion cycle, the ADC continues the current sample mode until the conversion completes and then switches to the new sample mode. Registers CONTROL and CONTROL_ACT update. Switching from a Continuous sample mode to a Single-shot mode triggers an extra conversion cycle. When using a GPIO Triggered sample mode, first configure the desired pin (A0 or A1) as an input by setting the SLOW_ALERT0[1:0] or GPIO_ALERT1[1:0] bits to 01b. 0000b = 8,192 sps (see Section 4.8.1) 0001b = 4,096 sps 0010b = 1,024 sps (default) 0011b = 256 sps 0100b = 64 sps 0101b = 8 sps (Slow mode) (see Section 4.2.8) 0110b = Single-shot mode (see Section 4.9.1) 0111b = Single-shot Average mode 1000b = Single-shot Awake mode 1001b = Single-shot Awake Average mode 1010b = VBUS Only at 16,384 sps (see Section 4.2.9) 1011b = VSENSE Only at 16,384 sps (see Section 4.2.9) 1100b = GPIO (A0) Triggered Single-shot Awake mode, Edge (see Section 4.9.1.4) 1101b = GPIO (A1) Triggered Single-shot Awake mode, Edge (see Section 4.9.1.4) 1110b = Sleep state (see Section 4.2.6) 1111b = Sleep state (see Section 4.2.6) |
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