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PAC1721 Datasheet(PDF) 59 Page - Microchip Technology |
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PAC1721 Datasheet(HTML) 59 Page - Microchip Technology |
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59 / 92 page ![]() 2026 Microchip Technology Inc. and its subsidiaries DS-20007088A-page 59 PAC1721 REGISTER 6-20: NEG_PWR_FSR (ADDRESS 13H) U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 – – – – CFG_VS[1:0] CFG_VB[1:0] bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as 0 -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared X = Bit is unknown This register is used to configure FSR for VBUS and/or VSENSE. Bipolar ranges for VBUS and VSENSE enable the measurement of bipolar voltages and currents. Issue a Refresh (any) command to copy NEG_PWR_FSR register settings to the NEG_PWR_FSR_ACT register. bit 7:4 Unimplemented at this time. Always reads 0. bit 3:2 CFG_VS[1:0]: Configure FSR for VSENSE measurements. 00b = VSENSE is in Unipolar 0-FSR mode: 0V to +100 mV FSR (default) 01b = VSENSE is in Bipolar ± FSR mode: –100 mV to +100 mV FSR 10b = VSENSE is in Bipolar ± FSR/2 mode: –50 mV to +50 mV FSR/2 11b = Reserved bit 1:0 CFG_VB[1:0]: Configure FSR for VBUS measurements. 00b = VBUS is in Unipolar 0-FSR mode: 0V to +9V FSR (default) 01b = VBUS is in Bipolar ± FSR mode: –9V to +9V FSR 10b = VBUS is in Bipolar ± FSR/2 mode: –4.5V to +4.5V FSR/2 11b = Reserved |
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