PAC1721 datasheet(28/92 Pages) MICROCHIP

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PAC1721

DS-20007088A-page 28

 2026 Microchip Technology Inc. and its subsidiaries

Pins A0/A1 are set as inputs during POR, allowing

signal detection to occur during the first I2C/SMBus

command. After the address is defined, pins A0/A1

enter their default state or are high impedance if the

defined address disallows multifunction operation.

To avoid blocking the SMBus, the Alert functionality is

disabled for addresses that do not include VDD pull-up

connections. The Slow function is allowed. However, it

remains disabled until the function is configured and

the SLOW pin is pulled high.

The following functionality can be changed when the

A0/A1 pins are pulled up to VDD through a resistor:

•A0 → SLOW, ALERT or GPIO

•A1 → SLOW, ALERT or GPIO

The correct programming workflow is:

Select the pin function

Configure pin settings

Enable the pin, if required

Use Case 1: A0 as SLOW Pin

POR → Set address → Set pin A0 to function as

SLOW pin

Note:

No setup required and no need to enable

the SLOW pin as it becomes active when

selecting the Slow function.

Use Case 2: A1 as GPIO Output Pin

POR → Set address → Set pin A1 to function as

GPIO output pin

Note:

No need to enable the GPIO pin as it

becomes active when selecting the GPIO

function.

Use Case 3: A0 as ALERT Pin

POR → Set address → Set pin A0 to function as

ALERT pin → Set alerts to be available on the

ALERT pin → Set limits → Enable ALERT pin as

output

External Alert Connections Considerations

Do not externally connect pins A0 and A1. While

this is technically feasible, considering the

power-up requirements for these pins, any

change in voltage during the initial address

setup results in an incorrect address definition

and incorrect A0/A1 functionality.

Do not enable any alerts until all PAC1721

devices that are part of the system have defined

addresses.

A single address, 1000 101b (R/W), has two

alerts available. The alerts cannot be set until

the I2C address is defined after the initial I2C

command.

5.1.2

SMBUS START CONDITION

The SMBus START condition is defined as a high-to-

low transition of the SMBus data line while the SMBus

clock line is pulled high.

5.1.3

SMBUS STOP CONDITION

The SMBus STOP condition is defined as a low-to-high

transition of the SMBus data line while the SMBus

clock line is pulled high.

While in communications with the SMBus protocol, if

PAC1721 detects an SMBus STOP condition, it resets

its target interface and prepares to receive further data.

5.1.4

SMBUS ACK AND NACK BITS

The SMBus target acknowledges (ACK) received data

bytes by holding the SMBus data line low after the

8th bit of each transmitted byte.

The SMBus target negatively acknowledges (NACK)

received data bytes by holding the SMBus data line

high after the 8th bit of each transmitted byte.

5.1.5

SMBUS DATA BYTES

All SMBus DATA bytes are sent MSB first. If a complete

set of SMBus clock pulses is not sent (for example, less

than 16 pulses for a 2-byte register), the data is written

starting from its MSB.

5.2

SMBus Timeout

PAC1721 supports the SMBus Timeout functionality.

This feature is disabled by default. To enable it, set the

TIMEOUT bit in the SMBUS_SETTINGS register to 1b.

If SMBus Timeout is enabled and the clock is held at

logic ‘0’ for 25 to 35 ms (tTIMEOUT), PAC1721 times out

and resets the SMBus interface. Communication is

restored with a START condition.

PAC1721 Datasheet(PDF) 28 Page - Microchip Technology

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