LPC2921 datasheet(36/81 Pages) PHILIPS

36 / 81 page

LPC2921_2923_2925_0

Preliminary data sheet

Rev. 00.01 — 24 October 2008

36 of 81

NXP Semiconductors

LPC2921/2923/2925

ARM9 microcontroller with CAN and LIN

Remark: Note that the ADC1 and ADC2 accept an input voltage up to of 3.6 V (see

Table 31) on the ADC1/2 IN pins. If the ADC is not used, the pins are 5 V tolerant.

6.14.4.3

Clock description

The ADC modules are clocked from two different sources; CLK_MSCSS_ADCx_APB and

CLK_ADCx (x = 1 or 2), see Section 6.7.2. Note that each ADC has its own CLK_ADCx

and CLK_MSCSS_ADCx_APB branch clocks for power management. If an ADC is

unused both its CLK_MSCSS_ADCx_APB and CLK_ADCx can be switched off.

The frequency of all the CLK_MSCSS_ADCx_APB clocks is identical to

CLK_MSCSS_APB since they are derived from the same base clock

BASE_MSCSS_CLK. Likewise the frequency of all the CLK_ADCx clocks is identical

since they are derived from the same base clock BASE_ADC_CLK.

The register interface towards the system bus is clocked by CLK_MSCSS_ADCx_APB.

Control logic for the analog section of the ADC is clocked by CLK_ADCx, see also

Figure 6.

6.14.5 Pulse Width Modulator (PWM)

The MSCSS in the LPC2921/2923/2925 includes four PWM modules with the following

features.

• Six pulse-width modulated output signals

• Double edge features (rising and falling edges programmed individually)

• Optional interrupt generation on match (each edge)

• Different operation modes: continuous or run-once

• 16-bit PWM counter and 16-bit prescale counter allow a large range of PWM periods

• A protective mode (TRAP) holding the output in a software-controllable state and with

optional interrupt generation on a trap event

• Three capture registers and capture trigger pins with optional interrupt generation on

a capture event

• Interrupt generation on match event, capture event, PWM counter overflow or trap

event

• A burst mode mixing the external carrier signal with internally generated PWM

• Programmable sync-delay output to trigger other PWM modules (master/slave

behavior)

Table 20.

Analog to digital converter pins

Symbol

Pin name

Direction

Description

ADC1/2 IN[7:0]

IN1/2[7:0]

analog input for 3.3 V ADC1/2, channel 7 to

channel 0

ADC2_EXT_START CAP1[2]

ADC external start-trigger input

VREFN

ADC LOW reference level

VREFP

ADC HIGH reference level

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