LPC2921 datasheet(24/81 Pages) PHILIPS

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LPC2921_2923_2925_0

Preliminary data sheet

Rev. 00.01 — 24 October 2008

24 of 81

NXP Semiconductors

LPC2921/2923/2925

ARM9 microcontroller with CAN and LIN

• Debug mode with disabling of reset

• Watchdog control register change-protected with key

• Programmable 32-bit watchdog timer period with programmable 32-bit prescaler.

6.12.2.1

Functional description

The watchdog timer consists of a 32-bit counter with a 32-bit prescaler.

The watchdog should be programmed with a time-out value and then periodically

restarted. When the watchdog times out, it generates a reset through the RGU.

To generate watchdog interrupts in watchdog debug mode the interrupt has to be enabled

via the interrupt enable register. A watchdog-overflow interrupt can be cleared by writing

to the clear-interrupt register.

Another way to prevent resets during debug mode is via the Pause feature of the

watchdog timer. The watchdog is stalled when the ARM9 is in debug mode and the

PAUSE_ENABLE bit in the watchdog timer control register is set.

The Watchdog Reset output is fed to the Reset Generator Unit (RGU). The RGU contains

a reset source register to identify the reset source when the device has gone through a

reset. See Section 6.15.4.

6.12.2.2

Clock description

The watchdog timer is clocked by two different clocks; CLK_SYS_PESS and CLK_SAFE,

see Section 6.7.2. The register interface towards the system bus is clocked by

CLK_SYS_PESS. The timer and prescale counters are clocked by CLK_SAFE which is

always on.

6.12.3 Timer

The LPC2921/2923/2925 contains six identical timers: four in the peripheral subsystem

and two in the Modulation and Sampling Control SubSystem (MSCSS) located at different

peripheral base addresses. This section describes the four timers in the peripheral

subsystem. Each timer has four capture inputs and/or match outputs. Connection to

device pins depends on the configuration programmed into the port function-select

registers. The two timers located in the MSCSS have no external capture or match pins,

but the memory map is identical, see Section 6.14.6. One of these timers has an external

input for a pause function.

The key features are:

• 32-bit timer/counter with programmable 32-bit prescaler

• Up to four 32-bit capture channels per timer. These take a snapshot of the timer value

when an external signal connected to the TIMERx CAPn input changes state. A

capture event may also optionally generate an interrupt

• Four 32-bit match registers per timer that allow:

– Continuous operation with optional interrupt generation on match

– Stop timer on match with optional interrupt generation

– Reset timer on match with optional interrupt generation

• Up to four external outputs per timer corresponding to match registers, with the

following capabilities:

LPC2921 Datasheet(PDF) 24 Page - NXP Semiconductors

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