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LPC2921 Datasheet(PDF) 55 Page - NXP Semiconductors |
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LPC2921 Datasheet(HTML) 55 Page - NXP Semiconductors |
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55 / 81 page ![]() LPC2921_2923_2925_0 © NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 — 24 October 2008 55 of 81 NXP Semiconductors LPC2921/2923/2925 ARM9 microcontroller with CAN and LIN 8. Static characteristics Table 31. Static characteristics VDD(CORE) =VDD(OSC_PLL) ; VDD(IO) = 2.7 V to 3.6 V; VDDA(ADC3V3) = 3.0 V to 3.6 V; Tvj =-40 °Cto+85 °C; all voltages are measured with respect to ground; positive currents flow into the IC; unless otherwise specified.[1] Symbol Parameter Conditions Min Typ Max Unit Supplies Core supply VDD(CORE) core supply voltage 1.71 1.80 1.89 V IDD(CORE) core supply current ARM9 and all peripherals active at max clock speeds -1.1 2.5 mA/ MHz all clocks off [2] -30 475 μA I/O supply VDD(IO) I/O supply voltage 2.7 - 3.6 V Oscillator/PLL supply VDD(OSC_PLL) oscillator and PLL supply voltage 1.71 1.80 1.89 V IDD(OSC_PLL) oscillator and PLL supply current normal mode - - 1 mA Power-down mode - - 2 μA Analog-to-digital converter supply VDDA(ADC3V3) 3.3 V ADC analog supply voltage 3.0 3.3 3.6 V IDDA(ADC3V3) 3.3 V ADC analog supply current normal mode - - 1.9 mA Power-down mode - - 4 μA Input pins and I/O pins configured as input VI input voltage all port pins and VDD(IO) applied see Section 7 [7][8] −0.5 - + 5.5 V port 0 pins 8 to 23 when ADC1/2 is used [8] VVREFP all port pins and VDD(IO) not applied −0.5 - +3.6 V all other I/O pins, RESET_N, TRST_N, TDI, JTAGSEL, TMS, TCK −0.5 - VDD(IO) V VIH HIGH-level input voltage all port pins, RESET_N, TRST_N, TDI, JTAGSEL, TMS, TCK 2.0 - - V VIL LOW-level input voltage all port pins, RESET_N, TRST_N, TDI, JTAGSEL, TMS, TCK -- 0.8 V Vhys hysteresis voltage 0.4 - - V ILIH HIGH-level input leakage current -- 1 μA ILIL LOW-level input leakage current -- 1 μA |
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