LPC2921 datasheet(43/81 Pages) PHILIPS

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LPC2921_2923_2925_0

Preliminary data sheet

Rev. 00.01 — 24 October 2008

43 of 81

NXP Semiconductors

LPC2921/2923/2925

ARM9 microcontroller with CAN and LIN

There are two primary clock generators: a low-power ring oscillator (LP_OSC) and a

crystal oscillator. See Figure 9.

LP_OSC is the source for the BASE_PCR_CLK that clocks the CGU itself and for

BASE_SAFE_CLK that clocks a minimum of other logic in the device (like the watchdog

timer). To prevent the device from losing its clock source LP_OSC cannot be put into

power-down. The crystal oscillator can be used as source for high-frequency clocks or as

an external clock input if a crystal is not connected.

Secondary clock generators are a PLL and seven fractional dividers (FDIV0..6). The PLL

has three clock outputs: normal, 120

° phase-shifted and 240° phase-shifted.

Configuration of the CGU0: For every output generator generating the base clocks a

choice can be made from the primary and secondary clock generators according to

Figure 10.

Fig 9.

Block diagram of the CGU0 (see Table 24 for all base clocks)

400 kHz LP_OSC

PLL

FDIV0

EXTERNAL

OSCLLLATOR

FDIV1

FDIV6

OUT 0

OUT 1

OUT 11

002aae147

clkout

clkout120

clkout240

CLOCK GENERATION UNIT (CGU0)

FREQUENCY

MONITOR

CLOCK

DETECTION

AHB TO DTL BRIDGE

BASE_SYS_CLK

BASE_ICLK1_CLK

OUT 3

BASE_IVNSS_CLK

OUT 2

BASE_PCR_CLK

BASE_SAFE_CLK

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