LPC2921 datasheet(12/81 Pages) PHILIPS

12 / 81 page

LPC2921_2923_2925_0

Preliminary data sheet

Rev. 00.01 — 24 October 2008

12 of 81

NXP Semiconductors

LPC2921/2923/2925

ARM9 microcontroller with CAN and LIN

6.6 Reset, debug, test, and power description

6.6.1 Reset and power-up behavior

The LPC2921/2923/2925 contains external reset input and internal power-up reset

circuits. This ensures that a reset is extended internally until the oscillators and flash have

reached a stable state. See Section 8 for trip levels of the internal power-up reset circuit1.

See Section 9 for characteristics of the several start-up and initialization times. Table 4

shows the reset pin.

At activation of the RST_N pin the JTAGSEL pin is sensed as logic LOW. If this is the case

the LPC2921/2923/2925 is assumed to be connected to debug hardware, and internal

circuits re-program the source for the BASE_SYS_CLK to be the crystal oscillator instead

of the Low-Power Ring Oscillator (LP_OSC). This is required because the clock rate when

running at LP_OSC speed is too low for the external debugging environment.

6.6.2 Reset strategy

The LPC2921/2923/2925 contains a central module, the Reset Generator Unit (RGU) in

the Power, Clock and Reset Subsystem (PCRSS), which controls all internal reset signals

towards the peripheral modules. The RGU provides individual reset control as well as the

monitoring functions needed for tracing a reset back to source.

6.6.3 IEEE 1149.1 interface pins (JTAG boundary-scan test)

The LPC2921/2923/2925 contains boundary-scan test logic according to IEEE 1149.1,

also referred to in this document as Joint Test Action Group (JTAG). The boundary-scan

test pins can be used to connect a debugger probe for the embedded ARM processor. Pin

JTAGSEL selects between boundary-scan mode and debug mode. Table 5 shows the

boundary- scan test pins.

Only for 1.8 V power sources

Table 4.

Reset pin

Symbol

Direction

Description

RST_N

external reset input, active LOW; pulled up internally

Table 5.

IEEE 1149.1 boundary-scan test and debug interface

Symbol

Description

JTAGSEL

TAP controller select input. LOW level selects ARM debug mode and HIGH level

selects boundary scan and flash programming; pulled up internally

TRST_N

test reset input; pulled up internally (active LOW)

TMS

test mode select input; pulled up internally

TDI

test data input, pulled up internally

TDO

test data output

TCK

test clock input

LPC2921 Datasheet(PDF) 12 Page - NXP Semiconductors

LPC2921 Datasheet(HTML) 12 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81

Datasheet Download

Link URL