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LPC2921 Datasheet(PDF) 15 Page - NXP Semiconductors |
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LPC2921 Datasheet(HTML) 15 Page - NXP Semiconductors |
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15 / 81 page  LPC2921_2923_2925_0 © NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 — 24 October 2008 15 of 81 NXP Semiconductors LPC2921/2923/2925 ARM9 microcontroller with CAN and LIN Table 7. Base clock and branch clock overview Base clock Branch clock name Parts of the device clocked by this branch clock Remark BASE_SAFE_CLK CLK_SAFE watchdog timer [1] BASE_SYS_CLK CLK_SYS_CPU ARM968E-S and TCMs CLK_SYS_SYS AHB bus infrastructure CLK_SYS_PCRSS AHB side of bridge in PCRSS CLK_SYS_FMC Flash-Memory Controller CLK_SYS_RAM0 Embedded SRAM Controller 0 (16 kB) CLK_SYS_RAM1 Embedded SRAM Controller 1 (16 kB) (LPC2925 only) CLK_SYS_GESS General Subsystem CLK_SYS_VIC Vectored Interrupt Controller CLK_SYS_PESS Peripheral Subsystem [2] [4] CLK_SYS_GPIO0 GPIO bank 0 CLK_SYS_GPIO1 GPIO bank 1 CLK_SYS_GPIO5 GPIO bank 5 CLK_SYS_IVNSS_A AHB side of bridge of IVNSS CLK_SYS_MSCSS_A AHB side of bridge of MSCSS CLK_SYS_DMA GPDMA CLK_SYS_USB USB registers BASE_PCR_CLK CLK_PCR_SLOW PCRSS, CGU, RGU and PMU logic clock [1], [3] BASE_IVNSS_CLK CLK_IVNSS_APB APB side of the IVNSS CLK_IVNSS_CANCA CAN controller Acceptance Filter CLK_IVNSS_CANC0 CAN channel 0 CLK_IVNSS_CANC1 CAN channel 1 CLK_IVNSS_I2C0 I2C0 CLK_IVNSS_I2C1 I2C1 CLK_IVNSS_LIN0 LIN channel 0 CLK_IVNSS_LIN1 LIN channel 1 BASE_MSCSS_CLK CLK_MSCSS_APB APB side of the MSCSS CLK_MSCSS_MTMR0 Timer 0 in the MSCSS CLK_MSCSS_MTMR1 Timer 1 in the MSCSS CLK_MSCSS_PWM0 PWM 0 CLK_MSCSS_PWM1 PWM 1 CLK_MSCSS_PWM2 PWM 2 CLK_MSCSS_PWM3 PWM 3 CLK_MSCSS_ADC1_APB APB side of ADC 1 CLK_MSCSS_ADC2_APB APB side of ADC 2 CLK_MSCSS_QEI Quadrature encoder |
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