LPC2921 datasheet(30/81 Pages) PHILIPS

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LPC2921_2923_2925_0

Preliminary data sheet

Rev. 00.01 — 24 October 2008

30 of 81

NXP Semiconductors

LPC2921/2923/2925

ARM9 microcontroller with CAN and LIN

6.13.2 LIN

The LPC2921/2923/2925 contain two LIN 2.0 master controllers. These can be used as

dedicated LIN 2.0 master controllers with additional support for sync break generation and

with hardware implementation of the LIN protocol according to spec 2.0.

The key features are:

• Complete LIN 2.0 message handling and transfer

• One interrupt per LIN message

• Slave response time-out detection

• Programmable sync-break length

• Automatic sync-field and sync-break generation

• Programmable inter-byte space

• Hardware or software parity generation

• Automatic checksum generation

• Fault confinement

• Fractional baud rate generator

6.13.2.1

Pin description

The two LIN 2.0 master controllers in the LPC2921/2923/2925 have the pins listed below.

The LIN pins are combined with other functions on the port pins of the

LPC2921/2923/2925. Table 18 shows the LIN pins. For more information see Ref. 1

subsection 3.43, LIN master controller.

Remark: Both LIN channels can be also configured as UART channels.

6.13.3 I2C-bus serial I/O controllers

The LPC2921/2923/2925 each contain two I2C-bus controllers.

The I2C-bus is bidirectional for inter-IC control using only two wires: a serial clock line

(SCL) and a serial data line (SDA). Each device is recognized by a unique address and

can operate as either a receiver-only device (e.g., an LCD driver) or as a transmitter with

the capability to both receive and send information (such as memory). Transmitters and/or

receivers can operate in either master or slave mode, depending on whether the chip has

to initiate a data transfer or is only addressed. The I2C is a multi-master bus, and it can be

controlled by more than one bus master connected to it.

The main features if the I2C-bus interfaces are:

• I2C0 and I2C1 use standard I/O pins with bit rates of up to 400 kbit/s (Fast I2C-bus)

and do not support powering off of individual devices connected to the same bus

lines.

• Easy to configure as master, slave, or master/slave.

Table 18.

LIN controller pins

Symbol

Pin name

Direction

Description

LIN0/1 TXD

TXDL0/1

OUT

LIN channel 0/1 transmit data output

LIN0/1 RXD

RXDL0/1

LIN channel 0/1 receive data input

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