LPC2921 datasheet(45/81 Pages) PHILIPS

45 / 81 page

LPC2921_2923_2925_0

Preliminary data sheet

Rev. 00.01 — 24 October 2008

45 of 81

NXP Semiconductors

LPC2921/2923/2925

ARM9 microcontroller with CAN and LIN

appropriate ‘CLK_SEL’ values are masked and unmasked accordingly. Each clock

detector can also generate interrupts at clock activation and deactivation so that the

system can be notified of a change in internal clock status.

Clock detection is done using a counter running at the BASE_PCR_CLK frequency. If no

positive clock edge occurs before the counter has 32 cycles of BASE_PCR_CLK the clock

is assumed to be inactive. As BASE_PCR_CLK is slower than any of the clocks to be

detected, normally only one BASE_PCR_CLK cycle is needed to detect activity. After

reset all clocks are assumed to be ‘non-present’, so the RDET status register will be

correct only after 32 BASE_PCR_CLK cycles.

Note that this mechanism cannot protect against a currently-selected clock going from

active to inactive state. Therefore an inactive clock may still be sent to the system under

special circumstances, although an interrupt can still be generated to notify the system.

Glitch-Free Switching: Provisions are included in the CGU to allow clocks to be

switched glitch-free, both at the output generator stage and also at secondary source

generators.

In the case of the PLL the clock will be stopped and held low for long enough to allow the

PLL to stabilize and lock before being re-enabled. For all non-PLL Generators the switch

will occur as quickly as possible, although there will always be a period when the clock is

held low due to synchronization requirements.

If the current clock is high and does not go low within 32 cycles of BASE_PCR_CLK it is

assumed to be inactive and is asynchronously forced low. This prevents deadlocks on the

interface.

6.15.2.2

PLL functional description

A block diagram of the PLL is shown in Figure 11. The input clock is fed directly to the

analog section. This block compares the phase and frequency of the inputs and generates

the main clock2. These clocks are either divided by 2

× P by the programmable post

divider to create the output clock, or sent directly to the output. The main output clock is

then divided by M by the programmable feedback divider to generate the feedback clock.

The output signal of the analog section is also monitored by the lock detector to signal

when the PLL has locked onto the input clock.

Generation of the main clock is restricted by the frequency range of the PLL clock input. See Table 32, Dynamic characteristics.

Fig 11. PLL block diagram

CCO

/ 2PDIV

P23

/ MDIV

002aad833

bypass

direct

clkout120

clkout240

clkout

input clock

PSEL bits

P23EN bit

MSEL bits

LPC2921 Datasheet(PDF) 45 Page - NXP Semiconductors

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