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LPC2921 Datasheet(PDF) 63 Page - NXP Semiconductors |
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LPC2921 Datasheet(HTML) 63 Page - NXP Semiconductors |
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63 / 81 page ![]() LPC2921_2923_2925_0 © NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 — 24 October 2008 63 of 81 NXP Semiconductors LPC2921/2923/2925 ARM9 microcontroller with CAN and LIN 9. Dynamic characteristics 9.1 Dynamic characteristics: I/O pins, internal clock, oscillators, PLL, and CAN [1] All parameters are guaranteed over the virtual junction temperature range by design. Pre-testing is performed at Tamb =125 °C ambient temperature on wafer level. Cased products are tested at Tamb =25 °C (final testing). Both pre-testing and final testing use correlated test conditions to cover the specified temperature and power supply voltage range. [2] See Table 24. [3] This parameter is not part of production testing or final testing, hence only a typical value is stated. [4] Oscillator start-up time depends on the quality of the crystal. For most crystals it takes about 1000 clock pulses until the clock is fully stable. Table 32. Dynamic characteristics VDD(CORE) =VDD(OSC_PLL); VDD(IO) = 2.7 V to 3.6 V; VDDA(ADC3V3) = 3.0 V to 3.6 V; all voltages are measured with respect to ground; positive currents flow into the IC; unless otherwise specified.[1] Symbol Parameter Conditions Min Typ Max Unit I/O pins tTHL HIGH-to-LOW transition time CL = 30 pF 4 - 13.8 ns tTLH LOW-to-HIGH transition time CL = 30 pF 4 - 13.8 ns Internal clock fclk(sys) system clock frequency [2] 10 - 125 MHz Tclk(sys) system clock period [2] 8 - 100 ns Low-power ring oscillator fref(RO) RO reference frequency 0.36 0.4 0.42 MHz tstartup start-up time at maximum frequency [3] -6 - μs Oscillator fi(osc) oscillator input frequency maximum frequency is the clock input of an external clock source applied to the Xin pin 10 - 100 MHz tstartup start-up time at maximum frequency [3] [4] -500 - μs PLL fi(PLL) PLL input frequency 10 - 25 MHz fo(PLL) PLL output frequency 10 - 160 MHz CCO; direct mode 156 - 320 MHz ta(clk) clock access time - - 63.4 ns ta(A) address access time - - 60.3 ns Jitter specification for CAN tjit(cc)(p-p) cycle to cycle jitter (peak-to-peak value) on CAN TXDC pin [3] -0.4 1 ns |
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