LPC2921 datasheet(46/81 Pages) PHILIPS

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LPC2921_2923_2925_0

Preliminary data sheet

Rev. 00.01 — 24 October 2008

46 of 81

NXP Semiconductors

LPC2921/2923/2925

ARM9 microcontroller with CAN and LIN

Triple output phases: For applications that require multiple clock phases two additional

clock outputs can be enabled by setting register P23EN to logic 1, thus giving three clocks

with a 120

° phase difference. In this mode all three clocks generated by the analog

section are sent to the output dividers. When the PLL has not yet achieved lock the

second and third phase output dividers run unsynchronized, which means that the phase

relation of the output clocks is unknown. When the PLL LOCK register is set the second

and third phase of the output dividers are synchronized to the main output clock CLKOUT

PLL, thus giving three clocks with a 120

° phase difference.

Direct output mode: In normal operating mode (with DIRECT set to logic 0) the CCO

clock is divided by 2, 4, 8 or 16 depending on the value on the PSEL[1:0] input, giving an

output clock with a 50 % duty cycle. If a higher output frequency is needed the CCO clock

can be sent directly to the output by setting DIRECT to logic 1. Since the CCO does not

directly generate a 50 % duty cycle clock, the output clock duty cycle in this mode can

deviate from 50 %.

Power-down control: A Power-down mode has been incorporated to reduce power

consumption when the PLL clock is not needed. This is enabled by setting the PD control

phase-frequency detector are stopped and the dividers enter a reset state. While in

Power-down mode the LOCK output is low, indicating that the PLL is not in lock. When

Power-down mode is terminated by clearing the PD control-register bit the PLL resumes

normal operation, and makes the LOCK signal high once it has regained lock on the input

clock.

6.15.2.3

Pin description

The CGU0 module in the LPC2921/2923/2925 has the pins listed in Table 25 below.

6.15.3 Clock generation for USB (CGU1)

The CGU1 block is functionally identical to the CGU0 block and generates the clock for

the USB interface and a dedicated output clock. The CGU1 block uses its own PLL and

fractional divider. The PLLs used in CGU0 and CGU1 are identical (see Section 6.15.2.2).

The clock input to the CGU1 PLL is provided by one of two base clocks generated in the

CGU0: BASE_ICLK0_CLK or BASE_ICLK1_CLK. The base clock not used for the PLL

can be configured to drive the output clock directly.

Table 25.

CGU0 pins

Symbol

Direction

Description

XOUT_OSC

OUT

Oscillator crystal output

XIN_OSC

Oscillator crystal input or external clock input

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