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LPC2921 Datasheet(PDF) 23 Page - NXP Semiconductors

Part # LPC2921
Description  ARM9 microcontroller with CAN, LIN, and USB device
PDF  81 Pages
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Manufacturer  PHILIPS [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

LPC2921 Datasheet(HTML) 23 Page - NXP Semiconductors

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LPC2921_2923_2925_0
© NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 00.01 — 24 October 2008
23 of 81
NXP Semiconductors
LPC2921/2923/2925
ARM9 microcontroller with CAN and LIN
6.11.4.1
Pin description
The event router module in the LPC2921/2923/2925 is connected to the pins listed below.
The pins are combined with other functions on the port pins of the LPC2921/2923/2925.
Table 12 shows the pins connected to the event router.
6.12 Peripheral subsystem
6.12.1 Peripheral subsystem clock description
The peripheral subsystem is clocked by a number of different clocks:
• CLK_SYS_PESS
• CLK_UART0/1
• CLK_SPI0/1/2
• CLK_TMR0/1/2/3
• CLK_SAFE see Section 6.7.2
6.12.2 Watchdog timer
The purpose of the watchdog timer is to reset the ARM9 processor within a reasonable
amount of time if the processor enters an error state. The watchdog generates a system
reset if the user program fails to trigger it correctly within a predetermined amount of time.
Key features:
• Internal chip reset if not periodically triggered
• Timer counter register runs on always-on safe clock
• Optional interrupt generation on watchdog time-out
Table 12.
Event-router pin connections
Symbol
Direction
Description
Default polarity
EXTINT 0 - 3
I
external interrupt input 0 - 3
1
CAN0 RXD
I
CAN0 receive data input wake-up
0
CAN1 RXD
I
CAN1 receive data input wake-up
0
I2C0_SCL
I
I2C0 SCL clock input
0
I2C1_SCL
I
I2C1 SCL clock input
0
USB_D+
I
USB D+ data input
<tbd>
LIN0 RXD
I
LIN0 receive data input wake-up
0
LIN1 RXD
I
LIN1 receive data input wake-up
0
SPI0 SDI
I
SPI0 receive data input
0
SPI1 SDI
I
SPI1 receive data input
0
SPI2 SDI
I
SPI2 receive data input
0
UART0 RXD
I
UART0 receive data input
0
UART1 RXD
I
UART1 receive data input
0
-
na
CAN interrupt (internal)
1
-
na
VIC FIQ (internal)
1
-
na
VIC IRQ (internal)
1



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