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LPC2921 Datasheet(PDF) 66 Page - NXP Semiconductors

Part # LPC2921
Description  ARM9 microcontroller with CAN, LIN, and USB device
PDF  81 Pages
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Manufacturer  PHILIPS [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

LPC2921 Datasheet(HTML) 66 Page - NXP Semiconductors

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LPC2921_2923_2925_0
© NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 00.01 — 24 October 2008
66 of 81
NXP Semiconductors
LPC2921/2923/2925
ARM9 microcontroller with CAN and LIN
9.4 Dynamic characteristics: SPI
[1]
All parameters are guaranteed over the virtual junction temperature range by design. Pre-testing is performed at Tamb =125 °C ambient
temperature on wafer level. Cased products are tested at Tamb =25 °C (final testing). Both pre-testing and final testing use correlated
test conditions to cover the specified temperature and power supply voltage range.
Table 35.
Dynamic characteristics of SPI pins
VDD(CORE) =VDD(OSC_PLL) ; VDD(IO) = 2.7 V to 3.6 V; VDDA(ADC3V3) = 3.0 V to 3.6 V; Tvj =-40 °Cto+85 °C; all voltages are
measured with respect to ground; positive currents flow into the IC; unless otherwise specified.[1]
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fSPI
SPI operating frequency
master operation
1
⁄
65024fclk(spi)
-
1
⁄
2fclk(spi)
MHz
slave operation
1
⁄
65024fclk(spi)
-
1
⁄
4fclk(spi)
MHz
SPI master
TSPICYC
SPI cycle time
-
<tbd>
<tbd>
<tbd>
ns
tSPICLKH
SPICLK HIGH time
-
<tbd>
<tbd>
<tbd>
ns
tSPICLKL
SPICLK LOW time
-
<tbd>
<tbd>
<tbd>
ns
tSPIDSU
SPI data set-up time
-
<tbd>
<tbd>
<tbd>
ns
tSPIDH
SPI data hold time
-
<tbd>
<tbd>
<tbd>
ns
tSPIQV
SPI data output valid time
-
<tbd>
<tbd>
<tbd>
ns
tSPIOH
SPI output data hold time
-
<tbd>
<tbd>
<tbd>
ns
SPI slave
-
TSPICYC
SPI cycle time
-
<tbd>
<tbd>
<tbd>
ns
tSPICLKH
SPICLK HIGH time
-
<tbd>
<tbd>
<tbd>
ns
tSPICLKL
SPICLK LOW time
-
<tbd>
<tbd>
<tbd>
ns
tSPIDSU
SPI data set-up time
-
<tbd>
<tbd>
<tbd>
ns
tSPIDH
SPI data hold time
-
<tbd>
<tbd>
<tbd>
ns
tSPIQV
SPI data output valid time
-
<tbd>
<tbd>
<tbd>
ns
tSPIOH
SPI output data hold time
-
<tbd>
<tbd>
<tbd>
ns
Fig 23.
SPI master timing (CPHA = 1)
SCK (CPOL = 0)
MOSI
MISO
002aad986
tSPICLK
tSPICLKH
tSPICLKL
tSPIDSU
tSPIDH
tSPIQV
DATA VALID
DATA VALID
tSPIOH
SCK (CPOL = 1)
DATA VALID
DATA VALID



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