ENC424J600 datasheet(30/168 Pages) MICROCHIP

30 / 168 page

ENC424J600/624J600

DS39935C-page 28

 2010 Microchip Technology Inc.

3.3

PHY Special Function Registers

The PHY registers provide configuration and control of

the PHY module, as well as status information about its

operation. These 16-bit registers are located in their

own memory space, outside of the main SFR space.

Unlike other SFRs, the PHY SFRs are not directly

accessible through the SPI or PSP interfaces. Instead,

access is accomplished through a special set of MAC

control registers that implement a Media Independent

Interface Management (MIIM) defined by IEEE 802.3;

these are the MICMD, MISTAT and MIREGADR

registers.

There are a total of 32 PHY addresses; however, only

10 locations implement user-accessible registers listed

in Table 3-8. Writes to unimplemented locations are

ignored and any attempts to read these locations return

FFFFh. Do not write to reserved PHY register locations

and ignore their content if read.

TABLE 3-8:

PHY SPECIAL FUNCTION

3.3.1

READING PHY REGISTERS

When a PHY register is read, the entire 16 bits are

obtained.

To read from a PHY register:

Write the address of the PHY register to read

from

into

the

MIREGADR

(Register 3-1). Make sure to also set reserved

bit 8 of this register.

Set the MIIRD bit (MICMD<0>, Register 3-2).

The read operation begins and the BUSY bit

(MISTAT<0>, Register 3-3) is automatically set

by hardware.

Wait 25.6

s. Poll the BUSY (MISTAT<0>) bit to

be certain that the operation is complete. While

busy, the host controller should not start any

MIISCAN operations or write to the MIWR

contents, the BUSY bit will clear itself.

Clear the MIIRD (MICMD<0>) bit.

Read the desired data from the MIRD register.

For 8-bit interfaces, the order that these bytes

are read is unimportant.

3.3.2

WRITING PHY REGISTERS

When a PHY register is written to, the entire 16 bits are

written at once; selective bit writes are not

implemented. If it is necessary to reprogram only select

bits in the register, the host microcontroller must first

read the PHY register, modify the resulting data and

then write the data back to the PHY register.

To write to a PHY register:

Write the address of the PHY register to write to

into the MIREGADR register. Make sure to also

set reserved bit 8 of this register.

Write the 16 bits of data into the MIWR register.

The low byte must be written first, followed by

the high byte.

Writing to the high byte of MIWR begins the

MIIM transaction and the BUSY (MISTAT<0>)

bit is automatically set by hardware.

The PHY register is written after the MIIM operation

completes, which takes 25.6

s. When the write opera-

tion has completed, the BUSY bit clears itself. The host

controller should not start any MIISCAN, MIWR or

MIIRD operations while the BUSY bit is set.

Address

Name

Address

Name

PHCON1

Reserved

PHSTAT1

PHCON2

Reserved

—

PHANA

Reserved

PHANLPA

Reserved

PHANE

Reserved

—17

Reserved

—18

—

—19

—

—1A

—

—1B

PHSTAT2

—1C

Reserved

—1D

Reserved

—

Reserved

—

PHSTAT3

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