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ENC424J600 Datasheet(PDF) 44 Page - Microchip Technology

Part # ENC424J600
Description  Stand-Alone 10/100 Ethernet Controller with SPI or Parallel Interface
PDF  168 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

ENC424J600 Datasheet(HTML) 44 Page - Microchip Technology

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ENC424J600/624J600
DS39935C-page 42
 2010 Microchip Technology Inc.
TABLE 4-2:
SINGLE BYTE INSTRUCTIONS
4.4
Two-Byte Instructions
There is only one instruction in the ENCX24J600 com-
mand set which uses two SPI bytes. The Read Bank
Select opcode, RBSEL, reads the internal SFR bank
select state and returns the value to the host controller.
Figure 4-2 shows the timing relationships for perform-
ing the two-byte operation. The first byte of the opcode
(‘11001000’) must be presented on the SI pin, MSb
first, followed by “don’t care” values for the second byte
(9th through 16th SCK rising edges). The bank select
value (00h through 03h) is returned on the SO pin, MSb
first, while the second byte is being presented on the SI
pin.
Because this instruction is a fixed length with no
optional parameters, it is possible to execute any
instruction following the execution of RBSEL without
deasserting the chip select line in between.
Since this opcode does not modify the ENCX24J600
internal state, it can be aborted at any time by returning
the CS pin to the inactive state.
FIGURE 4-2:
TWO-BYTE INSTRUCTION TIMING (RBSEL OPCODE)
Mnemonic
Opcode
Instruction
B0SEL
1100 0000
Selects SFR Bank 0
B1SEL
1100 0010
Selects SFR Bank 1
B2SEL
1100 0100
Selects SFR Bank 2
B3SEL
1100 0110
Selects SFR Bank 3
SETETHRST
1100 1010
Issues System Reset by setting ETHRST (ECON2<4>)
FCDISABLE
1110 0000
Disables flow control (sets ECON1<7:6> = 00)
FCSINGLE
1110 0010
Transmits a single pause frame (sets ECON1<7:6> = 01)
FCMULTIPLE
1110 0100
Enables flow control with periodic pause frames (sets ECON1<7:6> = 10)
FCCLEAR
1110 0110
Terminates flow control with a final pause frame (sets ECON1<7:6> = 11)
SETPKTDEC
1100 1100
Decrements PKTCNT by setting PKTDEC (ECON1<8>)
DMASTOP
1101 0010
Stops current DMA operation by clearing DMAST (ECON1<5>)
DMACKSUM
1101 1000
Starts DMA and checksum operation (sets ECON1<5:2> = 1000)
DMACKSUMS
1101 1010
Starts DMA checksum operation with seed (sets ECON1<5:2> = 1010)
DMACOPY
1101 1100
Starts DMA copy and checksum operation (sets ECON1<5:2> = 1100)
DMACOPYS
1101 1110
Starts DMA copy and checksum operation with seed (sets ECON1<5:2> = 1110)
SETTXRTS
1101 0100
Sets TXRTS (ECON1<1>), sends an Ethernet packet
ENABLERX
1110 1000
Enables packet reception by setting RXEN (ECON1<0>)
DISABLERX
1110 1010
Disables packet reception by clearing RXEN (ECON1<0>)
SETEIE
1110 1100
Enable Ethernet Interrupts by setting INT (ESTAT<15>)
CLREIE
1110 1110
Disable Ethernet Interrupts by clearing INT (ESTAT<15>)
CS
SCK
SI
SO
x
x
x
x
x
x
x
x
Hi-Z
Hi-Z
x
0
0
1
0
0
d
d
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
RBSEL
Opcode
SFR Bank Select
1
0
1
0
0
0
00



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