ENC424J600 datasheet(69/168 Pages) MICROCHIP

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 2010 Microchip Technology Inc.

DS39935C-page 67

ENC424J600/624J600

5.3.7

MODE 9

PSP Mode 9 is a 16-bit, fully-multiplexed mode that is

available on 64-pin devices only. The parallel interface

consists of 16 bidirectional data pins (AD<15:0>); the

lower 14 (AD<13:0>) also function as address pins. To

select PSP Mode 9, tie PSPCFG2 and PSPCFG3 to

VDD, while connecting PSPCFG1 to VSS. Figure 5-19

shows the connections required.

This mode uses an active-high Read (RD) strobe and

two Write (WRH and WRL) strobes in conjunction with

separate Chip Select (CS) and Address Latch (AL)

inputs. These five pins allow the host to select the

device, latch an address and then signal when a read

operation is desired or when valid data is being

presented to be written to either the low byte, high byte

or both. For proper operation while the ENCX24J600 is

selected, do not assert RD or AL while simultaneously

asserting either WRL or WRH.

AD<15:0> stay in a high-impedance state any time CS

or RD is low.

To perform a read operation:

Raise CS (if connected to the host).

Present the address to read from on AD<13:0>.

Strobe AL high, then low.

Set the host controller’s AD<15:0> bus pins as

inputs.

Raise RD.

The AD<15:0> bus begins driving out indeterminate

data for a brief period, then switches to the correct read

data after the appropriate read access time has

elapsed. When RD is lowered, the AD<15:0> pins

return to a high-impedance state.

The device always outputs a full 16 bits of data for each

read request. If only 8 bits of data are required, read the

data from the correct pins (AD<15:8> or AD<7:0>) and

discard the remaining byte.

To perform a write operation:

Raise CS (if connected to the host).

Present the address to write to on AD<13:0>.

Strobe AL.

If writing to the low byte of the memory location,

present the data on AD<7:0>, then strobe WRL

high, then low.

If writing to the high byte, present the data on

AD<15:8>, then strobe WRH.

If writing a whole word, strobe both WRL and

WRH simultaneously.

If a subsequent read or write of the same memory

address is desired, it is possible to restrobe RD, WRL

or WRH without going through another address latch

cycle.

Sample timing diagrams for reading and writing data in

this mode are provided in Figure 5-20 and Figure 5-21,

respectively.

FIGURE 5-19:

DEVICE CONNECTIONS FOR PSP MODE 9

Host MCU

ENC624J600

100 k



AD<15:0>

INT/SPISEL

PMD<15:0>

INTx(3)

PSPCFG1

PSPCFG2

PSPCFG3

CS(1)

WRL

PMCSx

PMRD

PMWRL

WRH(2)

PMWRH

(2)

PMALL

Note 1: Use of the CS strobe from the controller is optional. If not used, tie CS to VDD.

2: WRL and WRH may optionally be tied together to form a 16-bit write strobe. See Section 5.2.3 “Write Select

Pins” for details.

3: Use of the external interrupt signal to the controller is optional.

+3.3V

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