ENC424J600 datasheet(59/168 Pages) MICROCHIP

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 2010 Microchip Technology Inc.

DS39935C-page 57

ENC424J600/624J600

5.3.3

MODE 3

PSP Mode 3 is a 16-bit, fully demultiplexed mode that

is available on 64-pin devices only. The parallel inter-

face consists of 16 bidirectional data pins (AD<15:0>)

and 8 to 14 separate address pins (A<13:0>). To select

PSP Mode 3, tie PSPCFG3 and PSPCFG4 to VSS,

while connecting PSPCFG2 to VDD. Figure 5-7 shows

the connections required.

An active-high RD strobe and two Write strobes (WRH

and WRL) are utilized in conjunction with a separate

Chip Select (CS). These four pins allow the host to

select the device, then signal when a read operation is

desired or when valid data is being presented to be

written on either the low byte, high byte or both. For

proper operation, do not assert CS and RD while

simultaneously asserting either WRL or WRH.

In PSP Mode 3, AD<15:0> stay in a high-impedance

state any time CS or RD are low.

To perform a read operation:

Raise the CS line (if connected to the host).

Present the address to be read onto the address

bus.

Raise the RD strobe and wait the required time

for the access to occur.

When RD is raised high, the data bus begins driving out

indeterminate data for a brief period, then switches to

the correct read data after the appropriate read access

time has elapsed. When the RD strobe is lowered, the

data pins will return to a high-impedance state.

The device always outputs a full 16 bits of data for each

read request. If only 8 bits of data are required, read the

data from the correct pins (AD<15:8> or AD<7:0>) and

discard the remaining byte.

To perform a write operation:

Raise the CS line (if connected to the host).

Present the address onto the A<13:0> address

bus.

If writing to the low byte of the memory location,

present the data on AD<7:0>, and strobe the

WRL signal high and then low.

If writing to the high byte, present the data on the

AD<15:8> and strobe the WRH signal.

If writing a whole word, strobe both WRL and

WRH simultaneously.

Sample timing diagrams for reading and writing data in

this mode are provided in Figure 5-8 and Figure 5-9,

respectively.

FIGURE 5-7:

DEVICE CONNECTIONS FOR PSP MODE 3

Host MCU

ENC624J600

CS(1)

100 k



WRL

A<13:8>(3)

A<7:0>

AD<15:0>

INT/SPISEL

PMCSx

PMRD

PMWRL

PMA<13:8>

PMA<7:0>

PMD<15:0>

INTx(4)

PSPCFG2

PSPCFG3

PSPCFG4

Note 1:

Use of the CS strobe from the controller is optional. If not used, tie CS to VDD.

WRL and WRH may optionally be tied together to form a 16-bit write strobe. See Section 5.2.3 “Write Select

Pins”

for details.

Connect these pins when direct addressing of the entire SRAM buffer is required. Tie to VDD when only indirect

addressing is desired.

Use of the external interrupt signal to the controller is optional.

WRH(2)

PMWRH

(2)

+3.3V

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