ENC424J600 datasheet(80/168 Pages) MICROCHIP

Part #	ENC424J600

Description	Stand-Alone 10/100 Ethernet Controller with SPI or Parallel Interface

PDF	168 Pages

Scroll/Zoom	100%

Manufacturer	MICROCHIP [Microchip Technology]

Direct Link	http://www.microchip.com

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80 / 168 page

ENC424J600/624J600

DS39935C-page 78

 2010 Microchip Technology Inc.

bit 6

RXRST:

Receive Logic Reset bit

= Receive logic is held in Reset. RXEN (ECON1<0>) is automatically cleared by hardware when this

bit is set.

= Receive logic is not in Reset (normal operation)

bit 4

ETHRST:

Master Ethernet Reset bit

= All TX, RX, MAC, PHY, DMA, modular exponentiation, hashing and AES logic, and registers

(excluding COCON) are reset. Hardware self-clears this bit to ‘0’. After setting this bit, wait at least

s before attempting to read or write to the ENCX24J600 via the SPI or PSP interface.

= Device is not in Reset (normal operation)

bit 3-2

MODLEN<1:0>:

Modular Exponentiation Length Control bits

= Reserved

= 1024-bit modulus and operands

= 768-bit modulus and operands

= 512-bit modulus and operands

bit 1-0

AESLEN<1:0>:

AES Key Length Control bits

= Reserved

= 256-bit key

= 192-bit key

= 128-bit key

ECON2: ETHERNET CONTROL REGISTER 2 (CONTINUED)

Note 1:

Reset value on POR events only. All other Resets leave these bits unchanged.

ENC424J600 Datasheet(PDF) 80 Page - Microchip Technology