ENC424J600 datasheet(78/168 Pages) MICROCHIP

78 / 168 page

ENC424J600/624J600

DS39935C-page 76

 2010 Microchip Technology Inc.

8.6.1

PREPROGRAMMED MAC ADDRESS

As shipped, each ENCX24J600 device has been

preprogrammed with a unique MAC address. This

value is stored in nonvolatile memory and reloaded into

the MAADR registers after every Power-on and System

Reset. The factory preprogrammed MAC address is

permanent and will be restored to the MAC registers

after each Reset.

The preprogrammed address in nonvolatile memory

cannot be changed by the user, but it can be over-

written in the SFRs. If the user requires a different MAC

address value, the MAADR registers will need to be

written with the new MAC values by the host

application after each Reset.

8.7

PHY Initialization

Depending on the application, the PHY may need to be

configured during initialization. Typically, when using

auto-negotiation, users should write 0x05E1 to PHANA

to advertise flow control capability. Only special test

code, such as when attempting to do loopback tests,

needs other settings in the PHY to be reconfigured.

8.8

Other Considerations Following

Reset

Beyond the steps already described, there are addi-

tional configuration options that may need to be

adjusted following a device Reset. Normally, the default

configurations of these items on Power-on Reset do

not need to be changed.

For Half-Duplex mode:

• Verify that DEFER (MACON2<14>), BPEN

(MACON2<13>) and NOBKOFF (MACON2<12>)

are set correctly. These bits only apply when

operating in Half-Duplex mode; most applications

do not need to modify these settings from their

power-on defaults. For IEEE 802.3 compliance,

keep the DEFER bit set.

• Configure the Non-Back-to-Back Inter-Packet

Gap register, MAIPG (Register 8-5). Most applica-

tions program this register to 12h, which selects

maximum performance while complying with the

IEEE 802.3 IPG previously specified.

• Set the MAXRET<3:0> (MACLCON<3:0>) bits to

select the maximum number of retransmission

attempts after a collision is detected. Most

applications do not need to change this from the

default value.

For Full-Duplex mode:

• Configure the low byte of the Non-Back-to-Back

Inter-Packet Gap register, MAIPGL. Most applica-

tions program this register to 12h, which selects

maximum performance while complying with the

IEEE 802.3 IPG previously specified.

8.9

After Link Establishment

Several MAC configuration parameters are dependent

upon the current duplex mode of the link. Once

auto-negotiation completes, or the speed and duplex

modes are manually reconfigured, these registers must

updated

accordingly.

For

details

about

auto-negotiation

and

manual

speed/duplex

configuration, refer to Section 12.0 “Speed/Duplex

Configuration and Auto-Negotiation”

Once these steps are performed, packet reception is

re-enabled by setting RXEN (ECON1<0>). The host

controller may also begin to transmit packets as

described in Section 9.1 “Transmitting Packets”.

Before transmitting the first packet after link establish-

ment or auto-negotiation, the MAC duplex configuration

must be manually set to match the duplex configuration

of the PHY. To do this, configure FULDPX

(MACON2<0>) to match PHYDPX (ESTAT<10>).

For Half-Duplex mode, configure the Back-to-Back

Inter-Packet Gap register, MABBIPG (Register 8-4), to

set the nibble time offset delay between the end of one

transmission and the beginning of the next in a

back-to-back sequence. Program the register value as

the desired period in nibble times, minus 6. Most

applications will program this register to 12h, which

represents the minimum Inter-Packet Gap (IPG)

specified by IEEE 802.3, of 0.96

s (at 100 Mb/s) or

9.6

s (at 10 Mb/s).

For Full-Duplex mode, configure the Back-to-Back

Inter-Packet Gap register, MABBIPG, to set the nibble

time offset delay between the end of one transmission

and the beginning of the next in a back-to-back

sequence. The register value should be programmed

as the desired period in nibble times, minus 3. Most

applications will program this register to 15h, which

represents the minimum IEEE 802.3 specified

Inter-Packet Gap (IPG) of 0.96

s (at 100 Mb/s) or

9.6

s (at 10 Mb/s).

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