ENC424J600 datasheet(7/168 Pages) MICROCHIP

7 / 168 page

 2010 Microchip Technology Inc.

DS39935C-page 5

ENC424J600/624J600

1.0

DEVICE OVERVIEW

This document contains device-specific information for

the following devices:

• ENC424J600

• ENC624J600

The ENC424J600 and ENC624J600 are stand-alone,

Fast Ethernet controllers with an industry standard

Serial Peripheral Interface (SPI) or a flexible parallel

interface. They are designed to serve as an Ethernet

network interface for any microcontroller equipped with

SPI or a standard parallel port.

ENC424J600/624J600 devices meet all of the

IEEE 802.3 specifications applicable to 10Base-T and

100Base-TX

Ethernet,

including

many

optional

clauses, such as auto-negotiation. They incorporate a

number of packet filtering schemes to limit incoming

packets. They also provide an internal, 16-bit wide

DMA for fast data throughput and support for hardware

IP checksum calculations.

For applications that require the security and authenti-

cation features of SSL, TLS and other protocols related

to cryptography, a block of security engines is provided.

The engines perform RSA, Diffie-Hellman, AES, MD5

and SHA-1 algorithm computations, allowing reduced

code size, faster connection establishment and

throughput, and reduced firmware development effort.

Communication

with

the

microcontroller

implemented via the SPI or parallel interface, with data

rates ranging from 14 Mbit/s (SPI) to 160 Mbit/s

(demultiplexed, 16-bit parallel interface). Dedicated

pins are used for LED link and activity indication and for

transmit/receive/DMA interrupts.

A generous 24-Kbyte on-chip RAM buffer is available

for TX and RX operations. It may also be used by the

host microcontroller for general purpose storage.

Communication protocols, such as TCP, can use this

memory for saving data which may need to be

retransmitted.

For easy end product manufacturability, each

ENC624J600 family device is preprogrammed with a

unique nonvolatile MAC address. In most cases, this

allows the end device to avoid a serialized

programming step.

The

only

functional

difference

between

the

ENC424J600 (44-pin) and ENC624J600 (64-pin)

devices are the number of parallel interface options

they support. These differences, along with a summary

of their common features, are provided in Table 1-1. A

general block diagram for the devices is shown in

Figure 1-1.

A list of the pin features, sorted by function, is

presented in Table 1-2.

TABLE 1-1:

DEVICE FEATURES FOR ENC424J600/624J600

Feature

ENC424J600

ENC624J600

Pin Count

Ethernet Operating Speed

10/100 Mbps (auto-negotiate, auto-sense or manual)

Ethernet Duplex Modes

Half and Full (auto-negotiate and manual)

Ethernet Flow Control

Pause and Backpressure (auto and manual)

Buffer Memory (bytes)

24K (organized as 12K word x 16)

Internal Interrupt Sources

11 (mappable to a single external interrupt flag)

Serial Host Interface (SPI)

Yes

Parallel Host Interface:

Operating modes

Muliplexed,

8-bit

Yes

16-bit

Yes

Demultiplexed, 8-bit

Yes

16-bit

Yes

Cryptographic Security Options:

AES, 128/192/256-bit

Yes

MD5/SHA-1

Yes

Modular Exponentiation, 1024-bit

Yes

Receive Filter Options

Accept or reject packets with CRC match/mismatch, runt error collect

or reject, Unicast, Not-Me Unicast, Multicast, Broadcast,

Magic Packet™, Pattern Table and Hash Table

Packages

44-Pin TQFP, QFN

64-Pin TQFP

ENC424J600 Datasheet(PDF) 7 Page - Microchip Technology

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