ENC424J600 datasheet(20/168 Pages) MICROCHIP

20 / 168 page

ENC424J600/624J600

DS39935C-page 18

 2010 Microchip Technology Inc.

3.1.2

PSP INTERFACE MAPS

When one of the parallel interfaces is selected, the

memory map is very different from the SPI map. There

are two different memory address spaces (Figure 3-2):

• the main memory area

• the PHY register area

As in the serial memory map, the main memory area is

a linear, byte-addressable space of 32 Kbytes, with the

SRAM buffer located in the first 24-Kbyte region. The

cryptographic data memory is also mapped to the same

location as in the serial memory map. The main differ-

ence is that the SFRs are now located to an area with a

higher address than the cryptographic data space. Addi-

tional memory areas above the SFRs are reserved for

their accompanying Bit Set and Bit Clear registers.

Except for the cryptographic data memory, all

addresses in the main memory area are directly

accessible using the PSP bus. As with the serial inter-

face, the cryptographic memory can only be accessed

through the DMA.

The difference between the 8-bit and 16-bit interfaces is

how the SRAM buffer is addressed by the external

address bus. In 16-bit data modes, the address bus

treats the buffer as a 16-byte wide, word-addressable

space, spanning 000h to 3FFFh. In 8-bit data modes, the

address bus treats the buffer as an 8-bit, byte-address-

able space, ranging from 0000h to 7FFFh. In either case,

the SFRs used as memory pointers still address the

buffer as a byte-wide, byte-addressable space.

The PHY SFR space is implemented in the same

manner as the SPI interface described above.

In both 8-bit and 16-bit PSP modes, full device func-

tionality can be realized without using the full width of

the address bus. This is because the SRAM buffer can

still be read and written to by using SFR pointers. In

practical terms, this can allow designers in space or pin

constrained applications to only connect a subset of the

A or AD address pins to the host microcontroller. For

example, in the 8-Bit Multiplexed PSP Modes 5 or 6,

tying pins, AD<14:9> to VDD, still allows direct address

access to all SFRs. This reduces the number of pins

required for connection to the host controller, including

the interface control pins to 12 or 13.

FIGURE 3-2:

ENC424J600/624J600 MEMORY MAPS FOR PSP INTERFACES(1)

0000h

2FFFh

SRAM Buffer

Unimplemented

Cryptographic Data

(DMA access only)

3F00h

Unimplemented

Special Function Registers (R/W)

3F4Fh

0000h

5FFFh

7800h(2)

7C4Fh(2)

PSP Address Bus (Word Address)

Pointers (Byte Address)

16-Bit, MIIM Access Only

00h

1Fh

PHY Register Area

MIREGADR

3F80h

SFR Bit Set Registers

3FBFh

3FC0h

SFR Bit Clear Registers

3FFFh

16-Bit, MIIM Access Only

00h

1Fh

PHY Register Area

MIREGADR

0000h

5FFFh

SRAM Buffer

Unimplemented

7800h(2)

7C4Fh(2)

Cryptographic Data

(DMA access only)

7E00h

Unimplemented

Special Function

Registers (R/W)

7E9Fh

PSP Address Bus and

All Pointers

7F00h

SFR Bit Set Registers

7F7Fh

7F80h

SFR Bit Clear Registers

7FFFh

Main Area

8-Bit PSP

16-Bit PSP

Note 1:

Memory areas not shown to scale.

Addresses in this range are accessible only through internal address pointers of the DMA module.

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