ENC424J600 datasheet(48/168 Pages) MICROCHIP

48 / 168 page

ENC424J600/624J600

DS39935C-page 46

 2010 Microchip Technology Inc.

There are four banked SFR opcodes, summarized in

Table 4-4. Additional details for these opcodes are

provided below.

4.6.1.1

WCR

Opcode

The Write Control Register (WCR) opcode byte consists

of the prefix, ‘010’, concatenated with the 5-bit banked

SFR address of the first register to write to. For

example, if Bank 3 were currently selected and the host

microcontroller wanted to write to the ECON2L register

at banked address 0Eh, the 8-bit opcode would be

‘01001110’ or 4Eh.

Generally, WCR can be executed on most register

addresses, in any sequence and for any length. An

important exception is when WCR is used on any MAC

or MII register. These registers must be written as a

whole 16-bit register, low byte first (e.g., MACON1

must be written by first writing to MACON1L, then

MACON1H). Writing only to the upper byte of a MAC or

MII register results in a successful write to the upper

minate data. If a WCR instruction is aborted by raising

CS while writing to the upper byte of a MAC or MII

4.6.1.2

RCR

Opcode

The Read Control Register (RCR) opcode byte consists

of the prefix, ‘000’, concatenated with the 5-bit banked

SFR address of the first register to read from. Using the

previous example, the 8-bit opcode to read ECON2L

would be ‘00001110’ or 0Eh.

Read operations can be performed against any register

address, in any sequence and for any length. However,

due to volatile register shadowing, it is recommended

that the ERXHEADH:ERXHEADL register pair be read

in sequence (low byte first) to obtain the correct value.

See Section 9.2 “Receiving Packets” for additional

information.

4.6.1.3

BFS

and BFC Opcodes

The Bit Field Set (BFS) and Bit Field Clear (BFC)

opcodes consist of the prefix, ‘100’ (for BFS) or ‘101’

(for BFC), concatenated with the 5-bit banked SFR

address of the first register to write to. In terms of timing

and automatic address increment, they behave almost

identically to the WCR opcode. However, instead of

absolute data to be written to a register, the host

microcontroller provides a bit mask showing which bits

of the target register need to be set or cleared.

For BFS, the ENCX24J600 performs a logical OR

operation with the supplied bit field causing ‘1’ bits in the

bit field to become set bits in the register; ‘0’ bits in the bit

field have no effect on the corresponding register bits. For

BFC

, the ENCX24J600 performs a logical AND with the

complement of the supplied mask. This causes ‘1’ bits in

the mask to become clear bits in the register; ‘0’ bits in the

mask do not affect the corresponding register bits.

The host controller must use bit field operations when

attempting to change bits in a volatile control or interrupt

flag register. Normally, changing such a bit might be

accomplished

the

application

“read-modify-write” operation: reading the control regis-

ter’s contents, modifying the register copy in memory on

the controller side and writing the modified register data

back to the ENCX24J600. In a dynamic environment,

however, one or more control bits may change state

between the read and write, resulting in an incorrect

device state after the write. As an example, assume that

the DMA module is in use (ECON1L<5> = 1) at the

same time that the application wants to transmit a packet

(i.e.,

setting

ECON1L<1>).

the

time

read-modify-write on ECON1L is complete, the DMA

operation

may

have

completed

and

cleared

ECON1L<5>. In this case, the write back erroneously

starts a new DMA operation.

Using BFS and BFC allows for bit level changes to one

or more control bits without the delay of a read and

write back. In the previous example, using BFS with a

bit mask of ‘00000010’ on ECON1L, sets ECON1L<1>

and starts a packet transmission without affecting the

status of ECON1L<5>.

TABLE 4-4:

N-BYTE BANKED SFR INSTRUCTIONS

Note:

Unlike the WCR opcode, BFS and BFC

cannot be used to modify MAC or MII

registers. Never use these opcodes on

MAC and MII registers.

Instruction

Mnemonic

Opcode

Argument

1st Byte

2nd Byte

3rd Byte

Nth Byte

Read Control Register(s)

RCR

000a aaaa

xxxx xxxx

XXXX XXXX

Write Control Register(s)

WCR

010a aaaa

dddd dddd

DDDD DDDD

Bit Field(s) Set

BFS

100a aaaa

dddd dddd

DDDD DDDD

Bit Field(s) Clear

BFC

101a aaaa

dddd dddd

DDDD DDDD

Legend: x/X = read data (LSB/MSB), d/D = write data (LSB/MSB), a = banked SFR address.

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