ENC424J600 datasheet(12/168 Pages) MICROCHIP

12 / 168 page

ENC424J600/624J600

DS39935C-page 10

 2010 Microchip Technology Inc.

2.3

Voltage and Bias Pin

2.3.1

VDD AND VSS PINS

To reduce on-die noise levels and provide for the

high-current demands of Ethernet, there are many

power pins on ENC424J600/624J600 devices:

•VDD and VSS

•VDDOSC and VSSOSC

•VDDPLL and VSSPLL

•VDDRX and VSSRX

•VDDTX and VSSTX

Each VDD and VSS pin pair above should have a 0.1

F

ceramic bypass capacitor placed as close to the pins as

possible. For best EMI emission suppression, other

smaller capacitors, such as 0.001

F, should be placed

immediately across VDDTX/VSSTX and VDDPLL/VSSPLL.

All VDD power supply pins must be externally con-

nected to the same 3.3V ±10% power source. Similarly,

all VSS supply references must be externally connected

to the same ground node. If a ground connection

appears on two pins (e.g., VSSTX), connect both pins;

do not allow either to float. In addition, it is

recommended that the exposed bottom metal pad on

the 44-pin QFN package be tied to VSS.

Placing ferrite beads or inductors between any two of

the supply pins (e.g., between VDDOSC and VDDRX) is

not recommended. However, it is acceptable to isolate

all of the VDD supplies from the main circuit power sup-

ply through a single ferrite bead or inductor, if desired

for supply noise suppression reasons. Such isolation is

generally not necessary.

2.3.2

VCAP PIN

Most of the device’s digital logic operates at a nominal

1.8V. This voltage is supplied by an on-chip voltage

regulator, which generates the digital supply voltage

from the VDD rail. The only external component

required is an external filter capacitor, connected from

the VCAP pin to ground, as shown in Figure 2-3. A value

of at least 10

F is recommended.

The capacitor must also have a relatively low Equiva-

lent Series Resistance (ESR). It is recommended that

a low-ESR capacitor (ceramic, tantalum or similar)

should be used and high-ESR capacitors (such as

aluminum electrolytic) should be avoided.

The internal regulator is not designed to drive external

loads; therefore, do not attach other circuitry to VCAP.

FIGURE 2-3:

VCAP CONNECTIONS

2.3.3

RBIAS PIN

The internal analog circuitry in the PHY module

requires that an external 12.4 kΩ, 1% resistor be

attached from RBIAS to ground, as shown in

Figure 2-4. The resistor influences the TPOUT+/-

signal amplitude. The RBIAS resistor should be placed

as close as possible to the chip with no immediately

adjacent signal traces in order to prevent noise

capacitively coupling into the pin and affecting the

transmit behavior. It is recommended that the resistor

be a surface mount type.

FIGURE 2-4:

RBIAS RESISTOR

VDD

VCAP

VSS

ENCX24J600

F

3.3V

0.1

F

Regulator

+3.3V

I/O, PHY

+1.8V

Core, RAM,

MAC

RBIAS

ENCX24J600

12.4

k1%

PHY

ENC424J600 Datasheet(PDF) 12 Page - Microchip Technology

ENC424J600 Datasheet(HTML) 12 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL