PIC16LC771 datasheet(51/224 Pages) MICROCHIP

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DS41120C-page 51

PIC16C717/770/771

7.0

TIMER2 MODULE

The Timer2 module timer has the following features:

• 8-bit timer (TMR2 register)

• 8-bit period register (PR2)

• Readable and writable (Both registers)

• Software programmable prescaler (1:1, 1:4, 1:16)

• Software programmable postscaler (1:1 to 1:16)

• Interrupt on TMR2 match of PR2

• SSP module optional use of TMR2 output to gen-

erate clock shift

Timer2 has a control register, shown in Register 7-1.

Timer2 can be shut off by clearing control bit TMR2ON

(T2CON<2>) to minimize power consumption.

Figure 7-1 is a simplified block diagram of the Timer2

module.

Additional information on timer modules is available in

the PIC Mid-Range MCU Family Reference Manual,

(DS33023).

7.1

Timer2 Operation

Timer2 can be used as the PWM time-base for PWM

mode of the ECCP module.

The TMR2 register is readable and writable, and is

cleared on any device RESET.

The input clock (FOSC/4) has a prescale option of 1:1,

1:4 or 1:16, selected by control bits T2CKPS<1:0>

(T2CON<1:0>).

The match output of TMR2 goes through a 4-bit

postscaler (which gives a 1:1 to 1:16 scaling inclusive)

to generate a TMR2 interrupt (latched in flag bit

TMR2IF, (PIR1<1>)).

The prescaler and postscaler counters are cleared

when any of the following occurs:

• a write to the TMR2 register

• a write to the T2CON register

• any device RESET (Power-on Reset, MCLR

Reset, Watchdog Timer Reset, or Brown-out

Reset)

TMR2 is not cleared when T2CON is written.

TIMER2 CONTROL REGISTER (T2CON1: 12h)

U-0

R/W-0

—

TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0

bit 7

bit 0

bit 7

Unimplemented: Read as '0'

bit 6-3

TOUTPS<3:0>: Timer2 Output Postscale Select bits

0000

= 1:1 Postscale

0001

= 1:2 Postscale

•

1111

= 1:16 Postscale

bit 2

TMR2ON: Timer2 On bit

= Timer2 is on

= Timer2 is off

bit 1-0

T2CKPS<1:0>: Timer2 Clock Prescale Select bits

= Prescaler is 1

= Prescaler is 4

= Prescaler is 16

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

- n = Value at POR

’1’ = Bit is set

’0’ = Bit is cleared

x = Bit is unknown

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