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PIC16LC771 Datasheet(PDF) 93 Page - Microchip Technology |
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PIC16LC771 Datasheet(HTML) 93 Page - Microchip Technology |
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93 / 224 page  1999-2013 Microchip Technology Inc. Advance Information DS41120C-page 93 PIC16C717/770/771 9.2.16 CLOCK ARBITRATION Clock arbitration occurs when the master, during any receive, transmit or repeated START/STOP condition, de-asserts the SCL pin (SCL allowed to float high). When the SCL pin is allowed to float high, the baud rate generator (BRG) is suspended from counting until the SCL pin is actually sampled high. When the SCL pin is sampled high, the baud rate generator is reloaded with the contents of SSPADD<6:0> and begins counting. This ensures that the SCL high time will always be at least one BRG rollover count in the event that the clock is held low by an external device (Figure 9-22). FIGURE 9-22: CLOCK ARBITRATION TIMING IN MASTER TRANSMIT MODE SCL SDA BRG overflow, Release SCL, If SCL = 1 Load BRG with SSPADD<6:0>, and start count BRG overflow occurs, Release SCL, Slave device holds SCL low. SCL = 1 BRG starts counting clock high interval. SCL line sampled once every machine cycle (Tosc 4). Hold off BRG until SCL is sampled high. TBRG TBRG TBRG to measure high time interval |
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