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PIC16LC771 Datasheet(PDF) 12 Page - Microchip Technology |
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PIC16LC771 Datasheet(HTML) 12 Page - Microchip Technology |
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12 / 224 page  PIC16C717/770/771 DS41120C-page 12 1999-2013 Microchip Technology Inc. Bank 1 80h(3) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 23 81h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 15 82h(3) PCL Program Counter's (PC) Least Significant Byte 0000 0000 22 83h(3) STATUS IRP RP1 RP0 TO PD ZDC C 0001 1xxx 14 84h(3) FSR Indirect data memory address pointer xxxx xxxx 23 85h TRISA PORTA Data Direction Register 1111 1111 25 86h TRISB PORTB Data Direction Register 1111 1111 33 87h — Unimplemented — — 88h — Unimplemented — — 89h — Unimplemented — — 8Ah(1,3) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 22 8Bh(3) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 16 8Ch PIE1 —ADIE — — SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 17 8Dh PIE2 LVDIE — — —BCLIE — — — 0--- 0--- 19 8Eh PCON — — — —OSCF —POR BOR ---- 1-qq 21 8Fh — Unimplemented — — 90h — Unimplemented — — 91h SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 69 92h PR2 Timer2 Period Register 1111 1111 52 93h SSPADD Synchronous Serial Port (I2C mode) Address Register 0000 0000 76 94h SSPSTAT SMP CKE D/A PS R/W UA BF 0000 0000 66 95h WPUB PORTB Weak Pull-up Control 1111 1111 34 96h IOCB PORTB Interrupt on Change Control 1111 0000 34 97h P1DEL PWM 1 Delay value 0000 0000 62 98h — Unimplemented — — 99h — Unimplemented — — 9Ah — Unimplemented — — 9Bh REFCON VRHEN VRLEN VRHOEN VRLOEN — — — — 0000 ---- 102 9Ch LVDCON — — BGST LVDEN LVV3 LVV2 LVV1 LVV0 --00 0101 101 9Dh ANSEL — — Analog Channel Select --11 1111 25 9Eh ADRESL A/D Low Byte Result Register xxxx xxxx 107 9Fh ADCON1 ADFM VCFG2 VCFG1 VCFG0 — — — — 0000 ---- 107 TABLE 2-1: PIC16C717/770/771 SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Details on Page: Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'. Shaded locations are unimplemented, read as ‘0’. Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred to the upper byte of the program counter. 2: Other (non Power-up) Resets include external RESET through MCLR and Watchdog Timer Reset. 3: These registers can be addressed from any bank. |
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