PIC16LC771 datasheet(78/224 Pages) MICROCHIP

78 / 224 page

PIC16C717/770/771

DS41120C-page 78

Advance Information

 1999-2013 Microchip Technology Inc.

9.2.2.3

SLAVE RECEPTION

When the R/W bit of the address byte is clear

(SSPSR<0> = 0) and an address match occurs, the R/

W bit of the SSPSTAT register is cleared. The received

address is loaded into the SSPBUF register on the fall-

ing edge of the eighth SCL pulse.

When the address byte overflow condition exists, then

no Acknowledge (ACK) pulse is given. An overflow

condition is defined as either bit BF (SSPSTAT<0>) or

bit SSPOV (SSPCON<6>) is set.

An MSSP interrupt is generated for each data transfer

byte. Flag bit SSPIF (PIR1<3>) must be cleared in soft-

ware. The SSPSTAT register is used to determine the

status of the received byte.

TABLE 9-2:

DATA TRANSFER RECEIVED BYTE ACTIONS

FIGURE 9-8:

I2C SLAVE MODE WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)

Note:

The SSPBUF will be loaded if the SSPOV

bit is set and the BF flag is cleared. If a

read of the SSPBUF was performed, but

the user did not clear the state of the

SSPOV

bit

before

the

receive

occurred, the ACK is not sent and the SSP-

BUF is updated.

Status Bits as Data

Transfer is Received

SSPSR

SSPBUF

Generate ACK

Pulse

Set bit SSPIF

(SSP Interrupt occurs

if enabled)

SSPOV

Yes

Note 1: Shaded cells show the conditions where the user software did not properly clear the overflow condition.

A7 A6 A5 A4 A3 A2 A1

SDA

SCL

Bus Master

terminates

transfer

Bit SSPOV is set because the SSPBUF register is still full.

Cleared in software

SSPBUF register is read

ACK

Receiving Data

ACK

R/W=0

Receiving Address

SSPIF

BF (SSPSTAT<0>)

SSPOV (SSPCON<6>)

NACK

NACK is sent because of overflow

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