PIC16LC771 datasheet(71/224 Pages) MICROCHIP

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Advance Information

DS41120C-page 71

PIC16C717/770/771

When the application software is expecting to receive

valid data, the SSPBUF should be read before the next

byte of data to transfer is written to the SSPBUF. Buffer

full bit, BF (SSPSTAT<0>), indicates when the SSP-

BUF has been loaded with the received data (transmis-

sion is complete). When the SSPBUF is read, bit BF is

cleared. This data may be irrelevant if the SPI is only a

transmitter. Generally the MSSP Interrupt is used to

determine when the transmission/reception has com-

pleted. The SSPBUF must be read and/or written. If the

interrupt method is not going to be used, then software

polling can be done to ensure that a write collision does

not occur. Example 9-1 shows the loading of the SSP-

BUF (SSPSR) for data transmission.

EXAMPLE 9-1:

Loading the SSPBUF

(SSPSR) Register

The SSPSR is not directly readable or writable, and

can only be accessed by addressing the SSPBUF reg-

ister.

Additionally,

the

MSSP

STATUS

(SSPSTAT) indicates the various status conditions.

9.1.2

ENABLING SPI I/O

To enable the serial port, MSSP Enable bit, SSPEN

(SSPCON<5>) must be set. To reset or reconfigure SPI

mode, clear bit SSPEN, re-initialize the SSPCON reg-

isters, and then set bit SSPEN. This configures the

SDI, SDO, SCK and SS pins as serial port pins. For the

pins to behave as the serial port function, some must

have their data direction bits (in the TRIS register)

appropriately programmed. That is:

• SDI is automatically controlled by the SPI module

• SDO must have TRISB<5> cleared

• SCK (Master mode) must have TRISB<2>

cleared

• SCK (Slave mode) must have TRISB<2> set

•SS must have TRISB<1> set, and ANSEL<5>

cleared

Any serial port function that is not desired may be over-

ridden by programming the corresponding data direc-

tion (TRIS) register to the opposite value.

9.1.3

TYPICAL CONNECTION

Figure 9-2 shows a typical connection between two

microcontrollers. The master controller (Processor 1)

initiates the data transfer by sending the SCK signal.

Data is shifted out of both shift registers on their pro-

grammed clock edge, and latched on the opposite

edge of the clock. Both processors should be pro-

grammed to same Clock Polarity (SSPCON<4>), then

both controllers would send and receive data at the

same time. Whether the data is meaningful (or dummy

data) depends on the application software. This leads

to three scenarios for data transmission:

• Master sends data

—Slave sends dummy data

• Master sends data

—Slave sends data

• Master sends dummy data

—Slave sends data

FIGURE 9-2:

SPI MASTER/SLAVE CONNECTION

BSF

STATUS, RP0

;Specify Bank 1

LOOP BTFSS SSPSTAT, BF

;Has data been

;received

;(xmit complete)?

GOTO

LOOP

;No

BCF

STATUS, RP0

;Specify Bank 0

MOVF

SSPBUF, W

;Save SSPBUF...

MOVWF RXDATA

;...in user RAM

MOVF

TXDATA, W

;Get next TXDATA

MOVWF SSPBUF

;New data to xmit

Serial Input Buffer

(SSPBUF)

Shift Register

(SSPSR)

MSb

LSb

SDO

SDI

PROCESSOR 1

SCK

SPI Master SSPM<3:0> = 00xxb

Serial Input Buffer

(SSPBUF)

Shift Register

(SSPSR)

LSb

MSb

SDI

SDO

PROCESSOR 2

SCK

SPI Slave SSPM<3:0> = 010xb

Serial Clock

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