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PIC16LC771 Datasheet(PDF) 19 Page - Microchip Technology |
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PIC16LC771 Datasheet(HTML) 19 Page - Microchip Technology |
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19 / 224 page  1999-2013 Microchip Technology Inc. DS41120C-page 19 PIC16C717/770/771 2.2.2.6 PIE2 REGISTER This register contains the individual enable bits for the SSP bus collision and low voltage detect interrupts. REGISTER 2-6: PERIPHERAL INTERRUPT ENABLE REGISTER 2 (PIE2: 8Dh) R/W-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 LVDIE — — —BCLIE — — — bit 7 bit 0 bit 7 LVDIE: Low Voltage Detect Interrupt Enable bit 1 = LVD Interrupt is enabled 0 = LVD Interrupt is disabled bit 6-4 Unimplemented: Read as '0' bit 3 BCLIE: Bus Collision Interrupt Enable bit 1 = Bus Collision interrupt is enabled 0 = Bus Collision interrupt is disabled bit 2-0 Unimplemented: Read as '0' Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown |
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