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PIC16LC771 Datasheet(PDF) 53 Page - Microchip Technology |
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PIC16LC771 Datasheet(HTML) 53 Page - Microchip Technology |
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53 / 224 page ![]() 1999-2013 Microchip Technology Inc. DS41120C-page 53 PIC16C717/770/771 8.0 ENHANCED CAPTURE/ COMPARE/PWM (ECCP) MODULES The ECCP (Enhanced Capture/Compare/PWM) module contains a 16-bit register which can operate as a 16-bit capture register, as a 16-bit compare register or as a PWM master/slave Duty Cycle register. Table 8-1 shows the timer resources of the ECCP mod- ule modes. Capture/Compare/PWM Register1 (CCPR1) is com- prised of two 8-bit registers: CCPR1L (low byte) and CCPR1H (high byte). The CCP1CON and P1DEL reg- isters control the operation of ECCP. All are readable and writable. REGISTER 8-1: CCP1 CONTROL REGISTER (CCP1CON: 17h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PWM1M1 PWM1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 bit 7 bit 0 bit 7-6 PWM1M<1:0>: PWM Output Configuration CCP1M<3:2> = 00, 01, 10 xx = P1A assigned as Capture input, Compare output. P1B, P1C, P1D assigned as Port pins. CCP1M<3:2> = 11 00 = Single output. P1A modulated. P1B, P1C, P1D assigned as Port pins. 01 = Full-bridge output forward. P1D modulated. P1A active. P1B, P1C inactive. 10 = Half-bridge output. P1A, P1B modulated with deadband control. P1C, P1D assigned as Port pins. 11 = Full-bridge output reverse. P1B modulated. P1C active. P1A, P1D inactive. bit 5-4 DC1B<1:0>: PWM Duty Cycle Least Significant bits Capture Mode: Unused Compare Mode: Unused PWM Mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRnL. bit 3-0 CCP1M<3:0>: ECCP Mode Select bits 0000 = Capture/Compare/PWM off (resets ECCP module) 0001 = Unused (reserved) 0010 = Compare mode, toggle output on match (CCP1IF bit is set) 0011 = Unused (reserved) 0100 = Capture mode, every falling edge 0101 = Capture mode, every rising edge 0110 = Capture mode, every 4th rising edge 0111 = Capture mode, every 16th rising edge 1000 = Compare mode, set output on match (CCP1IF bit is set) 1001 = Compare mode, clear output on match (CCP1IF bit is set) 1010 = Compare mode, generate software interrupt on match (CCP1IF bit is set, CCP1 pin is unaffected) 1011 = Compare mode, trigger special event (CCP1IF bit is set; ECCP resets TMR1, and starts an A/D conversion, if the A/D module is enabled.) 1100 = PWM mode. P1A, P1C active high. P1B, P1D active high. 1101 = PWM mode. P1A, P1C active high. P1B, P1D active low. 1110 = PWM mode. P1A, P1C active low. P1B, P1D active high. 1111 = PWM mode. P1A, P1C active low. P1B, P1D active low. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown |
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