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PIC16LC771 Datasheet(PDF) 13 Page - Microchip Technology |
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PIC16LC771 Datasheet(HTML) 13 Page - Microchip Technology |
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13 / 224 page  1999-2013 Microchip Technology Inc. DS41120C-page 13 PIC16C717/770/771 Bank 2 100h(3) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 23 101h TMR0 Timer0 module’s register xxxx xxxx 45 102h(3) PCL Program Counter's (PC) Least Significant Byte 0000 0000 22 103h(3) STATUS IRP RP1 RP0 TO PD ZDC C 0001 1xxx 14 104h(3) FSR Indirect data memory address pointer xxxx xxxx 23 105h — Unimplemented — — 106h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xx11 33 107h — Unimplemented — — 108h — Unimplemented — — 109h — Unimplemented — — 10Ah(1,3) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 22 10Bh(3) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 16 10Ch PMDATL Program memory read data low xxxx xxxx 10Dh PMADRL Program memory read address low xxxx xxxx 10Eh PMDATH — — Program memory read data high --xx xxxx 10Fh PMADRH — — — — Program memory read address high ---- xxxx 110h- 11Fh — Unimplemented — — Bank 3 180h(3) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 23 181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 15 182h(3) PCL Program Counter's (PC) Least Significant Byte 0000 0000 22 183h(3) STATUS IRP RP1 RP0 TO PD ZDC C 0001 1xxx 14 184h(3) FSR Indirect data memory address pointer xxxx xxxx 23 185h — Unimplemented — — 186h TRISB PORTB Data Direction Register 1111 1111 33 187h — Unimplemented — — 188h — Unimplemented — — 189h — Unimplemented — — 18Ah(1,3) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 22 18Bh(3) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 16 18Ch PMCON1 Reserved — — — — — —RD 1--- ---0 18Dh- 18Fh — Unimplemented — — TABLE 2-1: PIC16C717/770/771 SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Details on Page: Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'. Shaded locations are unimplemented, read as ‘0’. Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred to the upper byte of the program counter. 2: Other (non Power-up) Resets include external RESET through MCLR and Watchdog Timer Reset. 3: These registers can be addressed from any bank. |
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