PIC16LC771 datasheet(91/224 Pages) MICROCHIP

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Advance Information

DS41120C-page 91

PIC16C717/770/771

9.2.14

ACKNOWLEDGE SEQUENCE

TIMING

An Acknowledge sequence is enabled by setting the

Acknowledge

sequence

enable

bit,

ACKEN

(SSPCON2<4>). When this bit is set, the SCL pin is

pulled low and the contents of the Acknowledge data bit

ACKDT (SSPCON2<5>) is presented on the SDA pin.

If the user wishes to generate an Acknowledge (ACK),

then the ACKDT bit should be cleared. Otherwise, the

user should set the ACKDT bit (NACK) before starting

an Acknowledge sequence. The baud rate generator is

then loaded from SSPADD<6:0> and counts for one

rollover period (TBRG). The SCL pin is then de-asserted

(pulled high). When the SCL pin is sampled high (clock

arbitration), the baud rate generator is reloaded and

counts for another TBRG. At the completion of the TBRG

period, the following events occur (see Figure 9-20):

• The SCL pin is pulled low.

• The ACKEN bit is automatically cleared.

• The baud rate generator is turned off.

• The MSSP module goes into IDLE mode.

9.2.14.1

WCOL STATUS FLAG

If the user writes the SSPBUF when an Acknowledge

sequence is in progress, the WCOL is set and the con-

tents of the buffer are unchanged (the write doesn’t

occur).

FIGURE 9-20:

ACKNOWLEDGE SEQUENCE WAVEFORM

Note: TBRG = one baud rate generator period.

SDA

SCL

SSPIF occurs at the

Acknowledge sequence starts here,

Write to SSPCON2

ACKEN automatically cleared

Cleared in

TBRG

end of receive

ACK

ACKEN = 1, ACKDT = 0

SSPIF

software

SSPIF occurs at the end

of Acknowledge sequence

Cleared in

software

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