PIC16LC771 datasheet(92/224 Pages) MICROCHIP

92 / 224 page

PIC16C717/770/771

DS41120C-page 92

Advance Information

 1999-2013 Microchip Technology Inc.

9.2.15

STOP CONDITION TIMING

The master asserts a STOP condition on the SDA and

SCL pins at the end of a receive/transmit by setting the

Stop Sequence Enable bit PEN (SSPCON2<2>). At the

end of a receive/transmit plus Acknowledge, the SCL

line is held low immediately following the falling edge of

the ninth SCL pulse. When the PEN bit is set, the mas-

ter will assert the SDA line low. When the SDA line is

sampled low, the baud rate generator is loaded from

SSPADD<6:0> and counts down to 0. When the baud

rate generator times out, the SCL pin is brought high,

the BRG is reloaded and one TBRG (baud rate genera-

tor rollover count) later, the SDA pin is de-asserted.

The SDA pin transition from low to high while SCL is

high is the STOP condition and causes the P bit (SSP-

STAT<4>) to be set. Following this the baud rage gen-

erator is reloaded with the contents of SSPADD<6:0>

and resumes its count. When the baud rate generator

times out (TBRG) the STOP condition is complete and

the PEN bit is cleared and the SSPIF bit is set

(Figure 9-21).

Whenever the firmware decides to take control of the

bus, it should first determine if the bus is busy by check-

ing the S and P bits in the SSPSTAT register. When the

MSSP module detects a START or STOP condition the

SSPIF flag is set. If the bus is busy (S bit is set), then

the CPU can be configured to be interrupted when

when the bus is free by enabling the SSPIF interrupt to

detect the STOP bit.

9.2.15.1

WCOL STATUS FLAG

If the user writes the SSPBUF when a STOP sequence

is in progress, then WCOL is set and the contents of the

buffer are unchanged (the write doesn’t occur).

FIGURE 9-21:

STOP CONDITION RECEIVE OR TRANSMIT MODE

SCL

SDA

SDA asserted low before rising edge of clock

Write to SSPCON2

Set PEN

Falling edge of

9th clock

SCL brought high after TBRG

Note: TBRG = one baud rate generator period.

TBRG

P bit (SSPSTAT<4>) is set

TBRG

to setup STOP condition.

NACK

TBRG

PEN bit (SSPCON2<2>) is cleared by

hardware and the SSPIF bit is set

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