PIC16LC771 datasheet(76/224 Pages) MICROCHIP

76 / 224 page

PIC16C717/770/771

DS41120C-page 76

Advance Information

 1999-2013 Microchip Technology Inc.

9.2

MSSP I2C Operation

The MSSP module in I2C mode fully implements all

master and slave functions (including general call sup-

port) and provides interrupts on START and STOP bits

in hardware to determine when the bus is free (multi-

master function). The MSSP module implements the

Standard mode specifications, as well as 7-bit and 10-

bit addressing.

Two pins are used to transfer data. They are the SCL

pin (clock) and the SDA pin (data). The MSSP module

functions are enabled by setting SSP Enable bit

SSPEN (SSPCON<5>). The SCL and SDA pins are

"glitch" filtered when operating as inputs. This filter

functions in both the 100 kHz and 400 kHz modes.

When these pins operate as outputs in the 100 kHz

mode, there is a slew rate control of the pin that is inde-

pendent of device frequency.

Before selecting any I2C mode, the SCL and SDA pins

must be programmed as inputs by setting the appropri-

ate TRIS bits. This allows the MSSP module to configure

and drive the I/O pins as required by the I2C protocol.

The MSSP module has six registers for I2C operation.

They are listed below.

• SSP Control Register (SSPCON)

• SSP Control Register2 (SSPCON2)

• SSP STATUS Register (SSPSTAT)

• Serial Receive/Transmit Buffer (SSPBUF)

• SSP Shift Register (SSPSR) - Not directly accessible

• SSP Address Register (SSPADD)

The SSPCON register allows for control of the I2C

operation. Four mode selection bits (SSPCON<3:0>)

configure the MSSP as any one of the following I2C

modes:

•I2C Slave mode (7-bit address)

•I2C Slave mode (10-bit address)

•I2C Master mode

SCL Freq = FOSC / [4

 (SSPADD + 1)]

• I2C Slave mode with START and STOP interrupts

(7-bit address)

• I2C Slave mode with START and STOP interrupts

(10-bit address)

• Firmware Controlled Master mode

The SSPSTAT register gives the status of the data

transfer. This information includes detection of a

START (S) or STOP (P) bit. It specifies whether the

received byte was data or address, if the next byte is

the completion of 10-bit address, and if this will be a

read or write data transfer.

SSPBUF is the register to which the transfer data is

written, and from which the transfer data is read. The

SSPSR register shifts the data in or out of the device.

In receive operations, the SSPBUF and SSPSR create

a doubled, buffered receiver. This allows reception of

the next byte to begin before reading the last byte of

received data. When the complete byte is received, it is

transferred from the SSPSR register to the SSPBUF

byte is received before the SSPBUF register is read a

receiver overflow occurs, in which case, the SSPOV bit

(SSPCON<6>) is set and the byte in the SSPSR is lost.

FIGURE 9-7:

I2C SLAVE MODE BLOCK

DIAGRAM

9.2.1

UPWARD COMPATIBILITY WITH

SSP MODULE

The MSSP module includes three SSP modes of oper-

ation to maintain upward compatibility with the SSP

module. These modes are:

• Firmware controlled Master mode (slave idle)

• 7-bit Slave mode with START and STOP

condition interrupts.

• 10-bit Slave mode with START and STOP

condition interrupts.

The firmware controlled Master mode enables the

START and STOP condition interrupts but all other I2C

functions are generated through firmware including:

• Generating the START and STOP conditions

• Generating the SCL clock

• Supplying the SDA bits in the proper time and

phase relationship to the SCL signal.

In firmware controlled Master mode, the SCL and SDA

lines are manipulated by clearing and setting the corre-

sponding TRIS bits. The output level is always low irre-

spective of the value(s) in the PORT register. A ‘1’ is

output by setting the TRIS bit and a ‘0’ is output by

clearing the TRIS bit

The 7-bit and 10-bit Slave modes with START and

STOP condition interrupts operate identically to the

MSSP Slave modes except that START and STOP

conditions generate SSPIF interrupts.

Read

Write

SSPSR reg

Match detect

SSPADD reg

START and

STOP bit detect

SSPBUF reg

Internal

Data Bus

Addr Match

Set, RESET

S, P bits

(SSPSTAT reg)

RB2/SCK/

Shift

Clock

MSb

LSb

SCL

RB4/SDI/

SDA

PIC16LC771 Datasheet(PDF) 76 Page - Microchip Technology

PIC16LC771 Datasheet(HTML) 76 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL