PIC16LC771 datasheet(20/224 Pages) MICROCHIP

20 / 224 page

PIC16C717/770/771

DS41120C-page 20

 1999-2013 Microchip Technology Inc.

2.2.2.7

PIR2 REGISTER

This register contains the SSP Bus Collision and low-

voltage detect interrupt flag bits.

PERIPHERAL INTERRUPT REGISTER 2 (PIR2: 0Dh)

Note:

Interrupt flag bits get set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the global

enable bit, GIE (INTCON<7>). User soft-

ware should ensure the appropriate inter-

rupt flag bits are clear prior to enabling an

interrupt.

R/W-0

U-0

R/W-0

U-0

LVDIF

—

—BCLIF

—

bit 7

bit 0

bit 7

LVDIF: Low Voltage Detect Interrupt Flag bit

= The supply voltage has fallen below the specified LVD voltage (must be cleared in software)

= The supply voltage is greater than the specified LVD voltage

bit 6-4

Unimplemented: Read as '0'

bit 3

BCLIF: Bus Collision Interrupt Flag bit

= A bus collision has occurred while the SSP module configured in I2C Master was

transmitting (must be cleared in software)

= No bus collision occurred

bit 2-0

Unimplemented: Read as '0'

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

- n = Value at POR

’1’ = Bit is set

’0’ = Bit is cleared

x = Bit is unknown

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