S25FS256S datasheet(103/154 Pages) SPANSION

103 / 154 page

November 6, 2013 S25FS-S_00_04

S25FS-S Family

103

Da ta

Shee t

(Prelim i nar y )

10.3.13

Write Any Register (WRAR 71h)

The Write Any Register (WRAR) command provides a way to write any device register - non-volatile or

volatile. The instruction is followed by a 3- or 4-byte address (depending on the address length configuration

CR2V[7], followed by one byte of data to write in the address selected register.

Before the WRAR command can be accepted by the device, a Write Enable (WREN) command must be

issued and decoded by the device, which sets the Write Enable Latch (WEL) in the Status Register to enable

any write operations. The WIP bit in SR1V may be checked to determine when the operation is completed.

The P_ERR and E_ERR bits in SR1V may be checked to determine if any error occurred during the

operation.

Some registers have a mixture of bit types and individual rules controlling which bits may be modified. Some

bits are read only, some are OTP.

Read only bits are never modified and the related bits in the WRAR command data byte are ignored without

setting a program or erase error indication (P_ERR or E_ERR in SR1V). Hence, the value of these bits in the

WRAR data byte do not matter.

OTP bits may only be programmed to the level opposite of their default state. Writing of OTP bits back to their

default state is ignored and no error is set.

Non-Volatile bits which are changed by the WRAR data, require non-volatile register write time (tW) to be

updated. The update process involves an erase and a program operation on the non-volatile register bits. If

either the erase or program portion of the update fails the related error bit and WIP in SR1V will be set to 1.

Volatile bits which are changed by the WRAR data, require the volatile register write time (tCS) to be updated.

Status Register 1 may be repeatedly read (polled) to monitor the Write-In-Progress (WIP) bit (SR1V[0]) and

the error bits (SR1V[6,5]) to determine when the register write is completed or failed. If there is a write failure,

the clear status command is used to clear the error status and enable the device to return to standby state.

However, the PPBL register can not be written by the WRAR command. Only the PPB Lock Bit Write

(PLBWR) command can write the PPBL register.

The command sequence and behavior is the same as the PP or 4PP command with only a single byte of data

provided. See Section 10.5.2, Page Program (PP 02h or 4PP 12h) on page 114.

The address map of the registers is the same as shown for Section 10.3.12, Read Any Register (RDAR 65h)

on page 101.

10.3.14

Set Burst Length (SBL C0h)

The Set Burst Length (SBL) command is used to configure the Burst Wrap feature. Burst Wrap is used in

conjunction with Quad I/O Read and DDR Quad I/O Read, in legacy SPI or QPI Mode, to access a fixed

length and alignment of data. Certain applications can benefit from this feature by improving the overall

system code execution performance. The Burst Wrap feature allows applications that use cache, to start

filling a cache line with instruction or data from a critical address first, then fill the remainder of the cache line

afterwards within a fixed length (8/16/32/64-bytes) of data, without issuing multiple read commands.

The Set Burst Length (SBL) command writes the CR4V register to enable or disable the wrapped read feature

and set the wrap boundary. When enabled the wrapped read feature changes the related read commands

from sequentially reading until the command ends, to reading sequentially wrapped within a group of bytes.

When CR4V[4]=1, the wrap mode is not enabled and unlimited length sequential read is performed.

When CR4V[4]=0, the wrap mode is enabled and a fixed length and aligned group of 8, 16, 32, or 64 bytes is

read starting at the byte address provided by the read command and wrapping around at the group alignment

boundary.

The group of bytes is of length and aligned on an 8-, 16-, 32-, or 64-byte boundary. CR4V[1:0] selects the

boundary. See Configuration Register 4 Volatile (CR4V) on page 72.

The starting address of the read command selects the group of bytes and the first data returned is the

addressed byte. Bytes are then read sequentially until the end of the group boundary is reached. If the read

continues the address wraps to the beginning of the group and continues to read sequentially. This wrapped

read sequence continues until the command is ended by CS# returning high.

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