S25FS256S datasheet(104/154 Pages) SPANSION

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104

S25FS-S Family

S25FS-S_00_04 November 6, 2013

Data

Sheet

(Pre limin ar y)

The Power-On Reset, hardware reset, or software reset default burst length can be changed by programming

CR4NV with the desired value using the WRAR command.

Figure 10.26 Set Burst Length Command Sequence

10.4

Read Memory Array Commands

Read commands for the main flash array provide many options for prior generation SPI compatibility or

enhanced performance SPI:

 Some commands transfer address or data on each rising edge of SCK. These are called Single Data Rate

commands (SDR).

 Some SDR commands transfer address one bit per rising edge of SCK and return data 1bit of data per

rising edge of SCK. These are called Single width commands.

 Some SDR commands transfer both address and data two or four bits per rising edge of SCK. These are

called Dual I/O for two bits, Quad I/O, and QPI for four bits. QPI also transfers instruction four bits per rising

edge.

 Some commands transfer address and data on both the rising edge and falling edge of SCK. These are

called Double Data Rate (DDR) commands.

 There are DDR commands for 4 bits of address or data per SCK edge. These are called Quad I/O DDR

and QPI DDR for four bit per edge transfer.

All of these commands, except QPI Read, begin with an instruction code that is transferred one bit per SCK

rising edge. QPI Read transfers the instruction four bits per SCK rising edge.The instruction is followed by

either a 3- or 4-byte address transferred at SDR or DDR. Commands transferring address or data 2 or 4 bits

per clock edge are called Multiple I/O (MIO) commands. For S25FS-S family devices at 256-Mbits or higher

density, the traditional SPI 3-byte addresses are unable to directly address all locations in the memory array.

Separate 4-byte address read commands are provided for access to the entire address space. These devices

may be configured to take a 4-byte address from the host system with the traditional 3-byte address

commands. The 4-byte address mode for traditional commands is activated by setting the Address Length bit

Table 10.4 Example Burst Wrap Sequences

CR4V[4,1:0]

Value (Hex)

Wrap

Boundary

(Bytes)

Start Address

(Hex)

Address Sequence (Hex)

Sequential

XXXXXX03

03, 04, 05, 06, 07, 08, 09, 0A, 0B, 0C, 0D, 0E, 0F, 10, 11, 12, 13, 14, 15, 16, 17, 18, ...

XXXXXX00

00, 01, 02, 03, 04, 05, 06, 07, 00, 01, 02, ...

XXXXXX07

07, 00, 01, 02, 03, 04, 05, 06, 07, 00, 01, ...

XXXXXX02

02, 03, 04, 05, 06, 07, 08, 09, 0A, 0B, 0C, 0D, 0E, 0F, 00, 01, 02, 03, ...

XXXXXX0C

0C, 0D, 0E, 0F, 00, 01, 02, 03, 02, 03, 04, 05, 06, 07, 08, 09, 0A, 0B, 0C, 0D, 0E, ...

XXXXXX0A

0A, 0B, 0C, 0D, 0E, 0F, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 1A, 1B, 1C, 1D, 1E, 1F, 00,

01, 02, 03, 04, 05, 06, 07, 08, 09, 0A, 0B, 0C, 0D, 0E, 0F, ...

XXXXXX1E

1E, 1F, 00, 01, 02, 03, 04, 05, 06, 07, 08, 09, 0A, 0B, 0C, 0D, 0E, 0F, 10, 11, 12, 13, 14, 15,

16, 17, 18, 19, 1A, 1B, 1C, 1D, 1E, 1F, 00, ...

XXXXXX03

03, 04, 05, 06, 07, 08, 09, 0A, 0B, 0C, 0D, 0E, 0F, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 1A,

1B, 1C, 1D, 1E, 1F, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 2A, 2B, 2C, 2D, 2E, 2F, 30, 31,

32, 33, 34, 35, 36, 37, 38, 39, 3A, 3B, 3C, 3D, 3E, 3F, 00, 01, 02 ...

XXXXXX2E

2E, 2F, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 3A, 3B, 3C, 3D, 3E, 3F, 00, 01, 02, 03, 04, 05,

06, 07, 08, 09, 0A, 0B, 0C, 0D, 0E, 0F, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 1A, 1B, 1C,

1D, 1E, 1F, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 2A, 2B, 2C, 2D, 2E, 2F, ...

CS#

SCLK

Phase

Instruction

Input Data

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