S25FS256S datasheet(106/154 Pages) SPANSION

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S25FS-S Family

S25FS-S_00_04 November 6, 2013

Data

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(Pre limin ar y)

10.4.2

Fast Read (FAST_READ 0Bh or 4FAST_READ 0Ch)

The instruction

 0Bh (CR2V[7]=0) is followed by a 3-byte address (A23-A0) or

 0Bh (CR2V[7]=1) is followed by a 4-byte address (A31-A0) or

 0Ch is followed by a 4-byte address (A31-A0)

The address is followed by dummy cycles depending on the latency code set in the Configuration Register

CR2V[3:0]. The dummy cycles allow the device internal circuits additional time for accessing the initial

address location. During the dummy cycles the data value on SO is “don’t care” and may be high impedance.

Then the memory contents, at the address given, are shifted out on SO.

The maximum operating clock frequency for Fast Read command is 133 MHz.

The address can start at any byte location of the memory array. The address is automatically incremented to

the next higher address in sequential order after each byte of data is shifted out. The entire memory can

therefore be read out with one single read instruction and address 000000h provided. When the highest

address is reached, the address counter will wrap around and roll back to 000000h, allowing the read

sequence to be continued indefinitely.

Figure 10.28 Fast Read (FAST_READ) Command Sequence (3-Byte Address, 0Bh [CR2V[7]=0)

Note:

1. A = MSB of address = 23 for CR2V[7]=0, or 31 for CR2V[7]=1 or command 0Ch.

10.4.3

Dual I/O Read (DIOR BBh or 4DIOR BCh)

The instruction

 BBh (CR2V[7]=0) is followed by a 3-byte address (A23-A0) or

 BBh (CR2V[7]=1) is followed by a 4-byte address (A31-A0) or

 BCh is followed by a 4-byte address (A31-A0)

The Dual I/O Read commands improve throughput with two I/O signals — IO0 (SI) and IO1 (SO). This

command takes input of the address and returns read data two bits per SCK rising edge. In some

applications, the reduced address input and data output time might allow for code execution in place (XIP) i.e.

directly from the memory device.

The maximum operating clock frequency for Dual I/O Read is 133 MHz.

The Dual I/O Read command has Continuous Read mode bits that follow the address so, a series of Dual I/O

Read commands may eliminate the 8-bit instruction after the first Dual I/O Read command sends a mode bit

pattern of Axh that indicates the following command will also be a Dual I/O Read command. The first Dual I/O

Read command in a series starts with the 8-bit instruction, followed by address, followed by four cycles of

mode bits, followed by an optional latency period. If the mode bit pattern is Axh the next command is

assumed to be an additional Dual I/O Read command that does not provide instruction bits. That command

starts with address, followed by mode bits, followed by optional latency.

Variable latency may be added after the mode bits are shifted into SI and SO before data begins shifting out

of IO0 and IO1. This latency period (dummy cycles) allows the device internal circuitry enough time to access

data at the initial address. During the dummy cycles, the data value on SI and SO are “don’t care” and may be

high impedance. The number of dummy cycles is determined by the frequency of SCK. The latency is

configured in CR2V[3:0].

The Continuous Read feature removes the need for the instruction bits in a sequence of read accesses and

greatly improves code execution (XIP) performance. The upper nibble (bits 7-4) of the Mode bits control the

CS#

SCK

Phase

Instruction

Address

Dummy Cycles

Data1

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