S25FS256S datasheet(108/154 Pages) SPANSION

108 / 154 page

108

S25FS-S Family

S25FS-S_00_04 November 6, 2013

Data

Sheet

(Pre limin ar y)

Figure 10.31 Dual I/O Continuous Read Command Sequence (4-Byte Address [CR2V[7]=1])

10.4.4

Quad I/O Read (QIOR EBh or 4QIOR ECh)

The instruction

 EBh (CR2V[7]=0) is followed by a 3-byte address (A23-A0) or

 EBh (CR2V[7]=1) is followed by a 4-byte address (A31-A0) or

 ECh is followed by a 4-byte address (A31-A0)

The Quad I/O Read command improves throughput with four I/O signals — IO0-IO3. It allows input of the

address bits four bits per serial SCK clock. In some applications, the reduced instruction overhead might

allow for code execution (XIP) directly from S25FS-S family devices. The Quad bit of the Configuration

The maximum operating clock frequency for Quad I/O Read is 133MHz.

For the Quad I/O Read command, there is a latency required after the mode bits (described below) before

data begins shifting out of IO0-IO3. This latency period (i.e., dummy cycles) allows the device’s internal

circuitry enough time to access data at the initial address. During latency cycles, the data value on IO0-IO3

are “don’t care” and may be high impedance. The number of dummy cycles is determined by the frequency of

SCK. The latency is configured in CR2V[3:0].

Following the latency period, the memory contents at the address given, is shifted out four bits at a time

through IO0-IO3. Each nibble (4 bits) is shifted out at the SCK frequency by the falling edge of the SCK

signal.

The address can start at any byte location of the memory array. The address is automatically incremented to

the next higher address in sequential order after each byte of data is shifted out. The entire memory can

therefore be read out with one single read instruction and address 000000h provided. When the highest

address is reached, the address counter will wrap around and roll back to 000000h, allowing the read

sequence to be continued indefinitely.

Address jumps can be done without the need for additional Quad I/O Read instructions. This is controlled

through the setting of the Mode bits (after the address sequence, as shown in Figure 10.32 on page 109 or

Figure 10.35 on page 110). This added feature removes the need for the instruction sequence and greatly

improves code execution (XIP). The upper nibble (bits 7-4) of the Mode bits control the length of the next

Quad I/O instruction through the inclusion or exclusion of the first byte instruction code. The lower nibble (bits

3-0) of the Mode bits are “don’t care” (“x”). If the Mode bits equal Axh, then the device remains in Quad I/O

High Performance Read mode and the next address can be entered (after CS# is raised high and then

asserted low) without requiring the EBh or ECh instruction, as shown in Figure 10.34 on page 109 or

Figure 10.36 on page 110; thus, eliminating eight cycles for the command sequence. The following

sequences will release the device from Quad I/O High Performance Read mode; after which, the device can

accept standard SPI commands:

1. During the Quad I/O Read Command Sequence, if the Mode bits are any value other than Axh,

then the next time CS# is raised high the device will be released from Quad I/O High Performance

Read mode.

2. Send the Mode Reset command.

Note that the two mode bit clock cycles and additional wait states (i.e., dummy cycles) allow the device’s

internal circuitry latency time to access the initial address after the last address cycle that is clocked into IO0-

IO3.

It is important that the IO0-IO3 signals be set to high-impedance at or before the falling edge of the first data

out clock. At higher clock speeds the time available to turn off the host outputs before the memory device

begins to drive (bus turn around) is diminished. It is allowed and may be helpful in preventing IO0-IO3 signal

CS#

SCK

IO0

IO1

Phase

DataN

Address

Mode

Dum

Data1

Data2

S25FS256S Datasheet(PDF) 108 Page - SPANSION

S25FS256S Datasheet(HTML) 108 Page - SPANSION

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL