S25FS256S datasheet(112/154 Pages) SPANSION

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S25FS-S Family

S25FS-S_00_04 November 6, 2013

Data

Sheet

(Pre limin ar y)

pattern was chosen to cover both “DC” and “AC” data transition scenarios. The two DC transition scenarios

include data low for a long period of time (two half clocks) followed by a high going transition (001) and the

complementary low going transition (110). The two AC transition scenarios include data low for a short period

of time (one half clock) followed by a high going transition (101) and the complementary low going transition

(010). The DC transitions will typically occur with a starting point closer to the supply rail than the AC

transitions that may not have fully settled to their steady state (DC) levels. In many cases the DC transitions

will bound the beginning of the data valid period and the AC transitions will bound the ending of the data valid

period. These transitions will allow the host controller to identify the beginning and ending of the valid data

eye. Once the data eye has been characterized the optimal data capture point can be chosen. See SPI DDR

Data Learning Registers on page 75 for more details.

In QPI Mode (CR2V[6]=1) the DDR Quad I/O instructions are sent 4 bits per SCK rising edge. The remainder

of the command protocol is identical to the DDR Quad I/O commands.

Figure 10.38 DDR Quad I/O Read Initial Access (3-Byte Address, EDh [CR2V[7]=0)

Figure 10.39 Continuous DDR Quad I/O Read Subsequent Access (3-Byte Address)

Figure 10.40 DDR Quad I/O Read Initial Access (4-Byte Address, EEh or EDh [CR2V[7]=1])

Note:

1. Example DLP of 34h (or 00110100).

CS#

SCK

IO0

IO1

IO2

IO3

Phase

20 16 12 8 4 0 4 0

7 6 5 4 3 2 1 0 4 0 4 0

21 17 13 9 5 1 5 1

7 6 5 4 3 2 1 0 5 1 5 1

22 18 14 10 6 2 6 2

7 6 5 4 3 2 1 0 6 2 6 2

23 19 15 11 7 3 7 3

7 6 5 4 3 2 1 0 7 3 7 3

Instruction

Address

Mode

Dummy

DLP

CS#

SCK

IO0

IO1

IO2

IO3

Phase

Address

Mode

Dummy

CS#

SCK

IO0

IO1

IO2

IO3

Phase

28 24 20 16 12 8 4 0 4 0

5 4

3 2 1 0

4 0 4 0

29 25 21 17 13 9 5 1 5 1

5 4

3 2 1 0

5 1 5 1

30 26 22 18 14 10 6 2 6 2

5 4

3 2 1 0

6 2 6 2

31 27 23 19 15 11 7 3 7 3

5 4

3 2 1 0

7 3 7 3

Instruction

Address

Mode

Dummy

DLP

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