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S25FS256S Datasheet(PDF) 113 Page - SPANSION

Part # S25FS256S
Description  MirrorBit Flash Non-Volatile Memory
PDF  154 Pages
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Manufacturer  SPANSION [SPANSION]
Direct Link  http://www.spansion.com
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S25FS256S Datasheet(HTML) 113 Page - SPANSION

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November 6, 2013 S25FS-S_00_04
S25FS-S Family
113
Da ta
Shee t
(Prelim i nar y )
Figure 10.41 DDR Quad I/O Read Initial Access
(4-Byte Address, EEh or EDh [CR2V[7]=1]) QPI Mode
Note:
1. Example DLP of 34h (or 00110100).
Figure 10.42 Continuous DDR Quad I/O Read Subsequent Access (4-Byte Address)
Note:
1. Example DLP of 34h (or 00110100).
10.5
Program Flash Array Commands
10.5.1
Program Granularity
10.5.1.1
Page Programming
Page Programming is done by loading a Page Buffer with data to be programmed and issuing a programming
command to move data from the buffer to the memory array. This sets an upper limit on the amount of data
that can be programmed with a single programming command. Page Programming allows up to a page size
(either 256 or 512 bytes) to be programmed in one operation. The page size is determined by the
Configuration Register bit CR3V[4]. The page is aligned on the page size address boundary. It is possible to
program from one bit up to a page size in each Page programming operation. It is recommended that a
multiple of 16-byte length and aligned Program Blocks be written. For the very best performance,
programming should be done in full pages of 512 bytes aligned on 512-byte boundaries with each Page being
programmed only once.
10.5.1.2
Single Byte Programming
Single Byte Programming allows full backward compatibility to the legacy standard SPI Page Programming
(PP) command by allowing a single byte to be programmed anywhere in the memory array.
CS#
SCLK
IO0
IO1
IO2
IO3
Phase
4
0
28 24 20 16 12
8
4
0
4
0
7
6
5
4
3
2
1
0
4
0
4
0
5
1
29 25 21 17 13
9
5
1
5
1
7
6
5
4
3
2
1
0
5
1
5
1
6
2
30 26 22 18 14 10
6
2
6
2
7
6
5
4
3
2
1
0
6
2
6
2
7
3
31 27 23 19 15 11
7
3
7
3
7
6
5
4
3
2
1
0
7
3
7
3
Instruct.
Address
Mode
Dummy
DLP
D1
D2
CS#
SCK
IO0
IO1
IO2
IO3
Phase
28 24
20 16
12
8
4
0
4
0
6
5 4
3
2
1 0
4
0
4
0
4
29 25
21 17
13
9
5
1
5
1
6
5 4
3
2
1 0
5
1
5
1
5
30 26
22 18
14 10
6
2
6
2
6
5 4
3
2
1 0
6
2
6
2
6
31 27
23 19
15 11
7
3
7
3
6
5 4
3
2
1 0
7
3
7
3
7
Address
Mode
Dummy
DLP
D1
D2



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