DAC39J84IAAVR datasheet(28/146 Pages) TI

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0.7V

0.25V

50pF

50O

TERM

=100

TERM

=001

TERM

=101

Level

Shift

RXP

RXN

Equalizer

Samplers

DAC39J84

SLASE48A – NOVEMBER 2014 – REVISED JANUARY 2015

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7.3 Feature Description

7.3.1 Serdes Input

The RX [7:0]P/N differential inputs are each internally terminated to a common point via 50

Ω, as shown in

Figure 55.

Figure 55. Serial Lane Input Termination

Common mode termination is via a 50pF capacitor to GND. The common mode voltage and termination of the

differential signal can be controlled in a number of ways to suit a variety of applications via rw_cfgrx0 [10:8]

(TERM), as described in Table 1.

(Note: AC coupling is recommended for JESD204B compliance.)

Table 1. Receiver Termination Selection

TERM

EFFECT

000

Reserved

001

Common point set to 0.7V. This configuration is for AC coupled systems. The transmitter has no effect on the receiver common

mode, which is set to optimize the input sensitivity of the receiver.

01x

Reserved

100

Common point set to GND. This configuration is for applications that require a 0V common mode.

101

Common point set to 0.25V. This configuration is for applications that require a low common mode.

110

Reserved

111

Common point floating. This configuration is for DC coupled systems in which the common mode voltage is set by the attached

transmit link parter to 0 and 0.6V. Note: this mode is not compatible with JESD204B.

Data input is sampled by the differential sensing amplifier using clocks derived from the clock recovery algorithm.

The polarity of RXP and RXN can be inverted by setting the INVPAIR [7:0] bit of the corresponding lane to “1”.

This can potentially simplify PCB layout and improve signal integrity by avoiding the need to swap over the

differential signal traces.

Due to processing effects, the devices in the RXP and RXN differential sense amplifiers will not be perfectly

matched and there will be some offset in switching threshold. DAC39J84 contains circuitry to detect and correct

for this offset. This feature can be enabled by setting the rw_cfgrx0 [23] (ENOC) bit to “1”. It is anticipated the

most users will enable this feature. During the compensation process, rw_cfgrx0 [25:24] (LOOPBACK) bit must

be set to “00”.

7.3.2 Serdes Rate

DAC39J84 has 8 configurable JESD204B serial lanes. The highest speed of each SerDes lane is 12.5Gbps.

Because the primary operating frequency of the SerDes is determined by its reference clock and PLL

multiplication factor, there is a limit on the lowest SerDes rate supported, refer to Table 2 for details. To support

lower speed application, each receiver should be configured to operate at half, quarter or eighth of the full rate

via rw_cfgrx0 [6:5] (RATE).

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