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DAC39J84IAAVR Datasheet(PDF) 64 Page - Texas Instruments

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Part # DAC39J84IAAVR
Description  DAC39J84 Quad-Channel, 16-Bit, 2.8 GSPS, Digital-to-Analog Converter with 12.5 Gbps JESD204B Interface
PDF  146 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

DAC39J84IAAVR Datasheet(HTML) 64 Page - Texas Instruments

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DAC39J84
SLASE48A – NOVEMBER 2014 – REVISED JANUARY 2015
www.ti.com
Table 30. Register Map (continued)
(MSB)
(LSB)
Name
Address
Default
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 15
Bit 0,
config32
0x20
0x0000
syncsel_dither(3:0)
reserved
syncsel_pap(3:0)
syncsel_fir5a(3:0)
config33
0x21
0x0000
reserved
config34
0x22
0x1B1B
patha_in_sel(1:0)
pathb_in_sel(1:0)
pathc_in_sel(1:0)
pathd_in_sel(1:0)
patha_out_sel(1:0)
pathb_out_sel(1:0)
pathc_out_sel(1:0)
pathd_out_sel(1:0)
config35
0x23
0xFFFF
sleep_cntl(15:0)
config36
0x24
0x0000
reserved
cdrvser_sysref_mode(2:0)
reserved
reserved
config37
0x25
0x0000
clkjesd_div(2:0)
reserved
reserved
reserved
reserved
reserved
config38
0x26
dither_ena(3:0)
dither_mixer_ena(3:0)
dither_sra_sel3:0)
reserved
reserved
dither _zero
config39
0x27
0x0000
reserved(15:0)
config40
0x28
0x0000
reserved(15:0)
config41
0x29
0x0000
reserved(15:0)
config42
0x2A
0x0000
reserved(15:0)
config43
0x2B
0x0000
reserved(15:0)
config44
0x2C
0x0000
reserved(15:0)
pap_
config45
0x2D
0x0000
reserved
reserved
pap_gain(2:0)
dlylen_sel
config46
0x2E
0xFFFF
pap_vth(15:0)
titest_dieid
config47
0x2F
0x0004
reserved
reserved
reserved
reserved
reserved
sifdac_ena
_read_ena
config48
0x30
0x0000
sifdac(15:0)
pll_ndivsync
config49
0x31
0x0000
lockdet_adj(2:0)
pll_reset
pll_ena
pll_cp(1:0)
pll_n(4:0)
memin_pll_lfvolt(2:0)
_ena
config50
0x32
0x0000
pll_m(7:0)
pll_p(3:0)
reserved
config51
0x33
0x0100
pll_vcosel
pll_vco(5:0)
pll_vcoitune(1:0)
pll_cp_adj(4:0)
reserved
syncb
syncb
syncb
syncb _lvds
_lvds
lvds
lvds
config52
0x34
0x0000
_lvds
_lvds
reserved
reserved
reserved(6:0)
_lpsel
_effuse
_sleep
_sub_ena
_lopwrb
_lopwra
_sel
config53
0x35
0x0000
reserved
reserved
reserved
reserved
config54
0x36
0x0000
reserved
config55
0x37
0x0000
reserved
config56
0x38
0x0000
reserved
config57
0x39
0x0000
reserved
config58
0x3A
0x0000
reserved
serdes
config59
0x3B
0x0000
serdes_refclk_div(3:0)
reserved
reserved
_clk_sel
config60
0x3C
0x0000
rw_cfgpll(15:0)
config61
0x3D
0x0000
reserved
rw_cfgrx0(14:0)
config62
0x3E
0x0000
rw_cfgrx0(15:0)
config63
0x3F
0x0000
reserved
INVPAIR(7:0)
config64
0x40
0x0000
reserved
config65
0x41
0x0000
errorcnt_link0(15:0)
config66
0x42
0x0000
errorcnt_link1(15:0)
64
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