DAC39J84IAAVR datasheet(60/146 Pages) TI

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DACCLKP

Divider

PFD &

DACCLKN

Internal Loop

Filter

External Loop

Filter

VCO

Prescaler

Divider

DACCLK

REFCLK

DAC39J84

SLASE48A – NOVEMBER 2014 – REVISED JANUARY 2015

www.ti.com

Device Functional Modes (continued)

The bypass mode is selected by setting the following:

1. pll_ena bit in register config49 to “0” to bypass the PLL circuitry.

2. pll_sleep bit in register config26 to “1” to put the PLL and VCO into sleep mode.

7.4.1.2 PLL Mode

In this mode the clock at the DACCLK input functions as a reference clock source to the on-chip PLL. The on-

chip PLL will then multiply this reference clock to supply a higher frequency DAC cores clock. Figure 79 shows

the block diagram of the PLL circuit, where N divider ratio ranges from 1 to 32, M divider ratio ranges from 1 to

256, and VCO prescaler divider from 2 to 18.

Figure 79. PLL Block Diagram

The DAC39J84 PLL mode is selected by setting the following:

1. pll_ena bit in register config49 to “1” to route to the PLL and clock path.

2. pll_sleep bit in register config26 to “0” to enable the PLL and VCO.

The output frequency of the VCO covers two frequency spans: H-band (4.44–5.6GHz) and L-band

(3.7–4.66GHz). When pll_vcosel in register config51 is “1”, the L-band is selected; when pll_vcosel is “0”, the

H-band is selected. At each band, the VCO range can be further adjusted by using the 6-bits pll_vco in register

config51. Figure 80 shows a typical relationship between the PLL VCO coarse tuning bits pll_vco and the VCO

center frequency. The corresponding equations for the H-band and L-band VCO are given in Equation 1 and

Equation 2, respectively. Note that It is recommended to shift pll_vco by +1 to guarantee the VCO operation at

hot temp environment. In case of cold temp environment, shift by -1 on the variable pll_vco is recommended.

H-Band: VCO Frequency (MHz) = 0.10998*pll_vco

2+10.574*pll_vco+4446.3,

(1)

where pll_vcosel = "0" and pll_vcoitune = "11".

L-Band: VCO Frequency (MHz) = 0.089703*pll_vco

2+8.8312*pll_vco+3752.5,

(2)

where pll_vcosel = "1" and pll_vcoitune = "10".

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