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DAC39J84IAAVR Datasheet(PDF) 97 Page - Texas Instruments

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Part # DAC39J84IAAVR
Description  DAC39J84 Quad-Channel, 16-Bit, 2.8 GSPS, Digital-to-Analog Converter with 12.5 Gbps JESD204B Interface
PDF  146 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

DAC39J84IAAVR Datasheet(HTML) 97 Page - Texas Instruments

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DAC39J84
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SLASE48A – NOVEMBER 2014 – REVISED JANUARY 2015
7.5.1.62 config61 Register – Address: 0x3D, Default: 0x0000
Figure 143. config61 Register Format
15
14
13
12
11
10
9
8
reserved
rw_cfgrx0
7
6
5
4
3
2
1
0
rw_cfgrx0
Table 92. config61 Register Field Descriptions
Register
Addr
Default
Bit
Name
Function
Name
(Hex)
Value
config61
0x3D
15
reserved
Reserved
0
14:0
rw_cfgrx0
Upper 15 bits of the configuration info for SerDes receivers.
000000000000000
Bit14:12
TESTPATT, Enables and selects verification of one of three
PRBS patterns, a user defined pattern or a clock test pattern.
Bit11
reserved
Bit10
reserved
Bit9:8
reserved
Bit7
ENOC, enable samplers offset compensation.
Bit6
EQHLD, hold the equalizer in its current status.
Bit5:3
EQ, enable and configure the equalizer to compensate the
loss in the transmission media.
Bit2:0
CDR, configure the clock/data recovery algorithm.
7.5.1.63 config62 Register – Address: 0x3E, Default: 0x0000
Figure 144. config62 Register Format
15
14
13
12
11
10
9
8
rw_cfgrx0
7
6
5
4
3
2
1
0
rw_cfgrx0
Table 93. config62 Register Field Descriptions
Register
Addr
Default
Bit
Name
Function
Name
(Hex)
Value
config62
0x3E
15:0
rw_cfgrx0
Lower 16 bits of the configuration info for SerDes receivers.
0x0000
Bit15:13
– LOS, enable loss of signal detection.
Bit12:11
– reserved.
Bit10:8
– TERM, select input termination options for serial lanes.
Note: AC coupling is recommended for JESD204B compliance.
Bit7
– reserved
Bit6:5
– RATE, operating rate, select full, half, quarter or eighth rate operation.
Bit4:2
– BUSWIDTH, select the parallel interface width (16 bit or 20bit). "010" -
20-bit; "011" - 16-bit
Note: 16bit is not compatible with JESD204B.
Bit1
SLEEPRX, powers the receiver down into sleep (fast power up) state
when high.
Bit0
– reserved.
Copyright © 2014–2015, Texas Instruments Incorporated
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