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DAC39J84IAAVR Datasheet(PDF) 98 Page - Texas Instruments

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Part # DAC39J84IAAVR
Description  DAC39J84 Quad-Channel, 16-Bit, 2.8 GSPS, Digital-to-Analog Converter with 12.5 Gbps JESD204B Interface
PDF  146 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

DAC39J84IAAVR Datasheet(HTML) 98 Page - Texas Instruments

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DAC39J84
SLASE48A – NOVEMBER 2014 – REVISED JANUARY 2015
www.ti.com
7.5.1.64 config63 Register – Address: 0x3F, Default: 0x0000
Figure 145. config63 Register Format
15
14
13
12
11
10
9
8
Not Used
7
6
5
4
3
2
1
0
INVPAIR
Table 94. config63 Register Field Descriptions
Register
Addr
Default
Bit
Name
Function
Name
(Hex)
Value
config63
0x3F
15:8
Not Used
Not Used
0x00
7:0
INVPAIR
Allows the PN pairs of the SerDes lanes to be inverted.
0x00
bit7 = lane7
bit6 = lane6
bit5 = lane5
bit4 = lane4
bit3 = lane3
bit2 = lane2
bit1 = lane1
bit0 = lane0
7.5.1.65 config64 Register – Address: 0x40, Default: 0x0000
Figure 146. config64 Register Format
15
14
13
12
11
10
9
8
reserved
7
6
5
4
3
2
1
0
reserved
Table 95. config64 Register Field Descriptions
Register
Addr
Default
Bit
Name
Function
Name
(Hex)
Value
config64
0x40
15:0
reserved
Reserved
0x0000
7.5.1.66 config65 Register – Address: 0x41, Default: 0x0000
Figure 147. config65 Register Format
15
14
13
12
11
10
9
8
errorcnt_ link0
7
6
5
4
3
2
1
0
errorcnt_ link0
Table 96. config65 Register Field Descriptions
Register
Addr
Default
Bit
Name
Function
Name
(Hex)
Value
config65
0x41
15:0
errorcnt_ link0
This is the error count for link0. What is counted as an error is determined
0x0000
by error_ena_link0. This is a 16bit value that is cleared when a JESD
READ
synchronization is performed or err_cnt_clr_link0 is programmed to a ‘1’.
ONLY
98
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Product Folder Links: DAC39J84



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